39 file_type : vhdlSource-2008
43 - wishbone_arbiter.vhdl
44 - wishbone_debug_master.vhdl
45 - wishbone_bram_wrapper.vhdl
52 file_type : vhdlSource-2008
59 - fpga/pp_soc_uart.vhd
60 - fpga/pp_utilities.vhd
61 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
62 file_type : vhdlSource-2008
66 - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
70 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
74 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
78 - fpga/nexys_a7.xdc : {file_type : xdc}
79 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
80 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
84 - fpga/nexys-video.xdc : {file_type : xdc}
85 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
86 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
90 - fpga/arty_a7.xdc : {file_type : xdc}
91 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
92 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
96 - fpga/cmod_a7-35.xdc : {file_type : xdc}
97 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
98 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
101 depend : [":microwatt:litedram"]
104 depend : [":microwatt:liteeth"]
107 depend : ["::uart16550"]
112 filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
118 - disable_flatten_core
123 vivado: {part : xc7a100tcsg324-1}
128 filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
134 - disable_flatten_core
135 - spi_flash_offset=10485760
140 vivado: {part : xc7a200tsbg484-1}
145 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
150 - disable_flatten_core
152 - spi_flash_offset=10485760
154 generate: [litedram_nexys_video]
156 vivado: {part : xc7a200tsbg484-1}
161 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
167 - disable_flatten_core
168 - spi_flash_offset=3145728
173 vivado: {part : xc7a35ticsg324-1L}
178 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
184 - disable_flatten_core
186 - spi_flash_offset=3145728
190 generate: [litedram_arty, liteeth_arty]
192 vivado: {part : xc7a35ticsg324-1L}
197 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
203 - disable_flatten_core
204 - spi_flash_offset=4194304
209 vivado: {part : xc7a100ticsg324-1L}
214 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
220 - disable_flatten_core
222 - spi_flash_offset=4194304
226 generate: [litedram_arty, liteeth_arty]
228 vivado: {part : xc7a100ticsg324-1L}
233 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
240 - disable_flatten_core
245 vivado: {part : xc7a35tcpg236-1}
249 filesets: [core, soc, xilinx_specific]
256 generator: litedram_gen
257 parameters: {board : arty}
260 generator: liteeth_gen
261 parameters: {board : arty}
263 litedram_nexys_video:
264 generator: litedram_gen
265 parameters: {board : nexys-video}
270 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
276 description : Initial on-chip RAM contents
281 description : External reset button polarity
286 description : Clock input frequency in HZ (for top-generic based boards)
292 description : Generated system clock frequency in HZ (for top-generic based boards)
296 disable_flatten_core:
298 description : Prevent Vivado from flattening the main core components
304 description : Use liteDRAM
310 description : Use liteEth
316 description : Use 16550-compatible UART from OpenCores
322 description : Enable second UART (always 16550-compatible)
328 description : No internal block RAM (only DRAM and init code carrying payload)
334 description : Offset (in bytes) in the SPI flash of the code payload to run
339 description : Length of the core log buffer in entries (32 bytes each)