microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  68       - fpga/fpga-random.xdc : {file_type : xdc}
  69
  70   debug_xilinx:
  71     files:
  72       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  73
  74   debug_dummy:
  75     files:
  76       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  77
  78   nexys_a7:
  79     files:
  80       - fpga/nexys_a7.xdc : {file_type : xdc}
  81       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  82       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  83
  84   nexys_video:
  85     files:
  86       - fpga/nexys-video.xdc : {file_type : xdc}
  87       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  88       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  89
  90   acorn_cle_215:
  91     files:
  92       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  93       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  94       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  95
  96   genesys2:
  97     files:
  98       - fpga/genesys2.xdc : {file_type : xdc}
  99       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 100       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 101
 102   arty_a7:
 103     files:
 104       - fpga/arty_a7.xdc : {file_type : xdc}
 105       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 106       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 107
 108   cmod_a7-35:
 109     files:
 110       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 111       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 112       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 113
 114   litedram:
 115       depend : [":microwatt:litedram"]
 116
 117   liteeth:
 118       depend : [":microwatt:liteeth"]
 119
 120   uart16550:
 121       depend : ["::uart16550"]
 122
 123 targets:
 124   nexys_a7:
 125     default_tool: vivado
 126     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 127     parameters :
 128       - memory_size
 129       - ram_init_file
 130       - clk_input
 131       - clk_frequency
 132       - disable_flatten_core
 133       - log_length=2048
 134       - uart_is_16550
 135       - has_fpu
 136     tools:
 137       vivado: {part : xc7a100tcsg324-1}
 138     toplevel : toplevel
 139
 140   acorn-cle-215-nodram:
 141     default_tool: vivado
 142     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 143     parameters :
 144       - memory_size
 145       - ram_init_file
 146       - clk_input
 147       - clk_frequency
 148       - disable_flatten_core
 149       - spi_flash_offset=10485760
 150       - log_length=2048
 151       - uart_is_16550
 152     tools:
 153       vivado: {part : xc7a200tsbg484-2}
 154     toplevel : toplevel
 155
 156   genesys2-nodram:
 157     default_tool: vivado
 158     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 159     parameters :
 160       - memory_size
 161       - ram_init_file
 162       - clk_frequency
 163       - use_litedram=false
 164       - no_bram=false
 165       - disable_flatten_core
 166       - spi_flash_offset=10485760
 167       - log_length=2048
 168       - uart_is_16550=false
 169     tools:
 170       vivado: {part : xc7k325tffg900-2}
 171     toplevel : toplevel
 172
 173   acorn-cle-215:
 174     default_tool: vivado
 175     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 176     parameters :
 177       - memory_size
 178       - ram_init_file
 179       - use_litedram=true
 180       - disable_flatten_core
 181       - no_bram
 182       - spi_flash_offset=10485760
 183       - log_length=2048
 184       - uart_is_16550
 185     generate: [litedram_acorn_cle_215]
 186     tools:
 187       vivado: {part : xc7a200tsbg484-2}
 188     toplevel : toplevel
 189
 190   genesys2:
 191     default_tool: vivado
 192     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 193     parameters :
 194       - memory_size
 195       - ram_init_file
 196       - use_litedram=true
 197       - disable_flatten_core
 198       - no_bram
 199       - spi_flash_offset=10485760
 200       - log_length=2048
 201       - uart_is_16550=false
 202     generate: [litedram_genesys2]
 203     tools:
 204       vivado: {part : xc7k325tffg900-2}
 205     toplevel : toplevel
 206
 207   nexys_video-nodram:
 208     default_tool: vivado
 209     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 210     parameters :
 211       - memory_size
 212       - ram_init_file
 213       - clk_input
 214       - clk_frequency
 215       - disable_flatten_core
 216       - spi_flash_offset=10485760
 217       - log_length=2048
 218       - uart_is_16550
 219       - has_fpu
 220     tools:
 221       vivado: {part : xc7a200tsbg484-1}
 222     toplevel : toplevel
 223
 224   nexys_video:
 225     default_tool: vivado
 226     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 227     parameters:
 228       - memory_size
 229       - ram_init_file
 230       - use_litedram=true
 231       - disable_flatten_core
 232       - no_bram
 233       - spi_flash_offset=10485760
 234       - log_length=2048
 235       - uart_is_16550
 236       - has_fpu
 237     generate: [litedram_nexys_video]
 238     tools:
 239       vivado: {part : xc7a200tsbg484-1}
 240     toplevel : toplevel
 241
 242   arty_a7-35-nodram:
 243     default_tool: vivado
 244     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 245     parameters :
 246       - memory_size
 247       - ram_init_file
 248       - clk_input
 249       - clk_frequency
 250       - disable_flatten_core
 251       - spi_flash_offset=3145728
 252       - log_length=512
 253       - uart_is_16550
 254       - has_uart1
 255       - has_fpu=false
 256     tools:
 257       vivado: {part : xc7a35ticsg324-1L}
 258     toplevel : toplevel
 259
 260   arty_a7-35:
 261     default_tool: vivado
 262     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 263     parameters :
 264       - memory_size
 265       - ram_init_file
 266       - use_litedram=true
 267       - use_liteeth=true
 268       - disable_flatten_core
 269       - no_bram
 270       - spi_flash_offset=3145728
 271       - log_length=512
 272       - uart_is_16550
 273       - has_uart1
 274       - has_fpu=false
 275     generate: [litedram_arty, liteeth_arty]
 276     tools:
 277       vivado: {part : xc7a35ticsg324-1L}
 278     toplevel : toplevel
 279
 280   arty_a7-100-nodram:
 281     default_tool: vivado
 282     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 283     parameters :
 284       - memory_size
 285       - ram_init_file
 286       - clk_input
 287       - clk_frequency
 288       - disable_flatten_core
 289       - spi_flash_offset=4194304
 290       - log_length=2048
 291       - uart_is_16550
 292       - has_uart1
 293       - has_fpu
 294     tools:
 295       vivado: {part : xc7a100ticsg324-1L}
 296     toplevel : toplevel
 297
 298   arty_a7-100:
 299     default_tool: vivado
 300     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 301     parameters:
 302       - memory_size
 303       - ram_init_file
 304       - use_litedram=true
 305       - use_liteeth=true
 306       - disable_flatten_core
 307       - no_bram
 308       - spi_flash_offset=4194304
 309       - log_length=2048
 310       - uart_is_16550
 311       - has_uart1
 312       - has_fpu
 313     generate: [litedram_arty, liteeth_arty]
 314     tools:
 315       vivado: {part : xc7a100ticsg324-1L}
 316     toplevel : toplevel
 317
 318   cmod_a7-35:
 319     default_tool: vivado
 320     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 321     parameters :
 322       - memory_size
 323       - ram_init_file
 324       - reset_low=false
 325       - clk_input=12000000
 326       - clk_frequency
 327       - disable_flatten_core
 328       - log_length=512
 329       - uart_is_16550
 330       - has_fpu=false
 331     tools:
 332       vivado: {part : xc7a35tcpg236-1}
 333     toplevel : toplevel
 334
 335   synth:
 336     filesets: [core, soc, xilinx_specific]
 337     tools:
 338       vivado: {pnr : none}
 339     toplevel: core
 340
 341 generate:
 342   litedram_arty:
 343     generator: litedram_gen
 344     parameters: {board : arty}
 345
 346   liteeth_arty:
 347     generator: liteeth_gen
 348     parameters: {board : arty}
 349
 350   litedram_nexys_video:
 351     generator: litedram_gen
 352     parameters: {board : nexys-video}
 353
 354   litedram_acorn_cle_215:
 355     generator: litedram_gen
 356     parameters: {board : acorn-cle-215}
 357
 358   litedram_genesys2:
 359     generator: litedram_gen
 360     parameters: {board : genesys2}
 361
 362 parameters:
 363   memory_size:
 364     datatype    : int
 365     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 366     paramtype   : generic
 367     default     : 16384
 368
 369   ram_init_file:
 370     datatype    : file
 371     description : Initial on-chip RAM contents
 372     paramtype   : generic
 373
 374   reset_low:
 375     datatype    : bool
 376     description : External reset button polarity
 377     paramtype   : generic
 378
 379   clk_input:
 380     datatype    : int
 381     description : Clock input frequency in HZ (for top-generic based boards)
 382     paramtype   : generic
 383     default     : 100000000
 384
 385   clk_frequency:
 386     datatype    : int
 387     description : Generated system clock frequency in HZ (for top-generic based boards)
 388     paramtype   : generic
 389     default     : 100000000
 390
 391   has_fpu:
 392     datatype    : bool
 393     description : Include a floating-point unit in the core
 394     paramtype   : generic
 395     default     : true
 396
 397   disable_flatten_core:
 398     datatype    : bool
 399     description : Prevent Vivado from flattening the main core components
 400     paramtype   : generic
 401     default     : false
 402
 403   use_litedram:
 404     datatype    : bool
 405     description : Use liteDRAM
 406     paramtype   : generic
 407     default     : false
 408
 409   use_liteeth:
 410     datatype    : bool
 411     description : Use liteEth
 412     paramtype   : generic
 413     default     : false
 414
 415   uart_is_16550:
 416     datatype    : bool
 417     description : Use 16550-compatible UART from OpenCores
 418     paramtype   : generic
 419     default     : true
 420
 421   has_uart1:
 422     datatype    : bool
 423     description : Enable second UART (always 16550-compatible)
 424     paramtype   : generic
 425     default     : false
 426
 427   no_bram:
 428     datatype    : bool
 429     description : No internal block RAM (only DRAM and init code carrying payload)
 430     paramtype   : generic
 431     default     : false
 432
 433   spi_flash_offset:
 434     datatype    : int
 435     description : Offset (in bytes) in the SPI flash of the code payload to run
 436     paramtype   : generic
 437
 438   log_length:
 439     datatype    : int
 440     description : Length of the core log buffer in entries (32 bytes each)
 441     paramtype   : generic