microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - execute1.vhdl
  23       - execute2.vhdl
  24       - loadstore1.vhdl
  25       - loadstore2.vhdl
  26       - multiply.vhdl
  27       - divider.vhdl
  28       - rotator.vhdl
  29       - writeback.vhdl
  30       - insn_helpers.vhdl
  31       - core.vhdl
  32       - icache.vhdl
  33       - plru.vhdl
  34       - cache_ram.vhdl
  35       - core_debug.vhdl
  36     file_type : vhdlSource-2008
  37
  38   soc:
  39     files:
  40       - wishbone_arbiter.vhdl
  41       - wishbone_debug_master.vhdl
  42       - soc.vhdl
  43     file_type : vhdlSource-2008
  44
  45   fpga:
  46     files:
  47       - fpga/pp_fifo.vhd
  48       - fpga/mw_soc_memory.vhdl
  49       - fpga/soc_reset.vhdl
  50       - fpga/pp_soc_uart.vhd
  51       - fpga/pp_utilities.vhd
  52       - fpga/toplevel.vhdl
  53       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  54     file_type : vhdlSource-2008
  55
  56   debug_xilinx:
  57     files:
  58       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  59
  60   debug_dummy:
  61     files:
  62       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  63
  64   nexys_a7:
  65     files:
  66       - fpga/nexys_a7.xdc : {file_type : xdc}
  67       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  68
  69   nexys_video:
  70     files:
  71       - fpga/nexys-video.xdc : {file_type : xdc}
  72       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  73
  74   arty_a7:
  75     files:
  76       - fpga/arty_a7.xdc : {file_type : xdc}
  77       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  78
  79   cmod_a7-35:
  80     files:
  81       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  82       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  83
  84 targets:
  85   nexys_a7:
  86     default_tool: vivado
  87     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  88     parameters :
  89       - memory_size
  90       - ram_init_file
  91       - clk_input
  92       - clk_frequency
  93     tools:
  94       vivado: {part : xc7a100tcsg324-1}
  95     toplevel : toplevel
  96
  97   nexys_video:
  98     default_tool: vivado
  99     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 100     parameters :
 101       - memory_size
 102       - ram_init_file
 103       - clk_input
 104       - clk_frequency
 105     tools:
 106       vivado: {part : xc7a200tsbg484-1}
 107     toplevel : toplevel
 108
 109   arty_a7-35:
 110     default_tool: vivado
 111     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 112     parameters :
 113       - memory_size
 114       - ram_init_file
 115       - clk_input
 116       - clk_frequency
 117     tools:
 118       vivado: {part : xc7a35ticsg324-1L}
 119     toplevel : toplevel
 120
 121   arty_a7-100:
 122     default_tool: vivado
 123     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 124     parameters :
 125       - memory_size
 126       - ram_init_file
 127       - clk_input
 128       - clk_frequency
 129     tools:
 130       vivado: {part : xc7a100ticsg324-1L}
 131     toplevel : toplevel
 132
 133   cmod_a7-35:
 134     default_tool: vivado
 135     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 136     parameters :
 137       - memory_size
 138       - ram_init_file
 139       - reset_low=false
 140       - clk_input=12000000
 141     tools:
 142       vivado: {part : xc7a35tcpg236-1}
 143     toplevel : toplevel
 144
 145   synth:
 146     filesets: [core, soc]
 147     tools:
 148       vivado: {pnr : none}
 149     toplevel: core
 150
 151 parameters:
 152   memory_size:
 153     datatype    : int
 154     description : On-chip memory size (bytes)
 155     paramtype   : generic
 156
 157   ram_init_file:
 158     datatype    : file
 159     description : Initial on-chip RAM contents
 160     paramtype   : generic
 161
 162   reset_low:
 163     datatype    : bool
 164     description : External reset button polarity
 165     paramtype   : generic
 166
 167   clk_input:
 168     datatype    : int
 169     description : Clock input frequency in HZ (for top-generic based boards)
 170     paramtype   : generic
 171     default     : 100000000
 172
 173   clk_frequency:
 174     datatype    : int
 175     description : Generated system clock frequency in HZ (for top-generic based boards)
 176     paramtype   : generic
 177     default     : 50000000