microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - multiply.vhdl
  31       - divider.vhdl
  32       - rotator.vhdl
  33       - writeback.vhdl
  34       - insn_helpers.vhdl
  35       - core.vhdl
  36       - icache.vhdl
  37       - plru.vhdl
  38       - cache_ram.vhdl
  39       - core_debug.vhdl
  40       - utils.vhdl
  41     file_type : vhdlSource-2008
  42
  43   soc:
  44     files:
  45       - wishbone_arbiter.vhdl
  46       - wishbone_debug_master.vhdl
  47       - wishbone_bram_wrapper.vhdl
  48       - soc.vhdl
  49       - xics.vhdl
  50       - syscon.vhdl
  51     file_type : vhdlSource-2008
  52
  53   fpga:
  54     files:
  55       - fpga/main_bram.vhdl
  56       - fpga/soc_reset.vhdl
  57       - fpga/pp_fifo.vhd
  58       - fpga/pp_soc_uart.vhd
  59       - fpga/pp_utilities.vhd
  60       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  61     file_type : vhdlSource-2008
  62
  63   debug_xilinx:
  64     files:
  65       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  66
  67   debug_dummy:
  68     files:
  69       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  70
  71   nexys_a7:
  72     files:
  73       - fpga/nexys_a7.xdc : {file_type : xdc}
  74       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  75       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  76
  77   nexys_video:
  78     files:
  79       - fpga/nexys-video.xdc : {file_type : xdc}
  80       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  81       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  82
  83   arty_a7:
  84     files:
  85       - fpga/arty_a7.xdc : {file_type : xdc}
  86       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  87       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  88
  89   cmod_a7-35:
  90     files:
  91       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  92       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  93       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  94
  95   litedram:
  96       depend : [":microwatt:litedram"]
  97
  98 targets:
  99   nexys_a7:
 100     default_tool: vivado
 101     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
 102     parameters :
 103       - memory_size
 104       - ram_init_file
 105       - clk_input
 106       - clk_frequency
 107       - disable_flatten_core
 108     tools:
 109       vivado: {part : xc7a100tcsg324-1}
 110     toplevel : toplevel
 111
 112   nexys_video-nodram:
 113     default_tool: vivado
 114     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 115     parameters :
 116       - memory_size
 117       - ram_init_file
 118       - clk_input
 119       - clk_frequency
 120       - disable_flatten_core
 121     tools:
 122       vivado: {part : xc7a200tsbg484-1}
 123     toplevel : toplevel
 124
 125   nexys_video:
 126     default_tool: vivado
 127     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
 128     parameters:
 129       - memory_size
 130       - ram_init_file
 131       - use_litedram=true
 132       - disable_flatten_core
 133     generate: [dram_nexys_video]
 134     tools:
 135       vivado: {part : xc7a200tsbg484-1}
 136     toplevel : toplevel
 137
 138   arty_a7-35-nodram:
 139     default_tool: vivado
 140     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 141     parameters :
 142       - memory_size
 143       - ram_init_file
 144       - clk_input
 145       - clk_frequency
 146       - disable_flatten_core
 147     tools:
 148       vivado: {part : xc7a35ticsg324-1L}
 149     toplevel : toplevel
 150
 151   arty_a7-35:
 152     default_tool: vivado
 153     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 154     parameters :
 155       - memory_size
 156       - ram_init_file
 157       - use_litedram=true
 158       - disable_flatten_core
 159     generate: [dram_arty]
 160     tools:
 161       vivado: {part : xc7a35ticsg324-1L}
 162     toplevel : toplevel
 163
 164   arty_a7-100-nodram:
 165     default_tool: vivado
 166     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 167     parameters :
 168       - memory_size
 169       - ram_init_file
 170       - clk_input
 171       - clk_frequency
 172       - disable_flatten_core
 173     tools:
 174       vivado: {part : xc7a100ticsg324-1L}
 175     toplevel : toplevel
 176
 177   arty_a7-100:
 178     default_tool: vivado
 179     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 180     parameters:
 181       - memory_size
 182       - ram_init_file
 183       - use_litedram=true
 184       - disable_flatten_core
 185     generate: [dram_arty]
 186     tools:
 187       vivado: {part : xc7a100ticsg324-1L}
 188     toplevel : toplevel
 189
 190   cmod_a7-35:
 191     default_tool: vivado
 192     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 193     parameters :
 194       - memory_size
 195       - ram_init_file
 196       - reset_low=false
 197       - clk_input=12000000
 198       - clk_frequency
 199       - disable_flatten_core
 200     tools:
 201       vivado: {part : xc7a35tcpg236-1}
 202     toplevel : toplevel
 203
 204   synth:
 205     filesets: [core, soc]
 206     tools:
 207       vivado: {pnr : none}
 208     toplevel: core
 209
 210 generate:
 211   dram_arty:
 212     generator: litedram_gen
 213     parameters: {board : arty}
 214
 215   dram_nexys_video:
 216     generator: litedram_gen
 217     parameters: {board : nexys-video}
 218
 219 parameters:
 220   memory_size:
 221     datatype    : int
 222     description : On-chip memory size (bytes)
 223     paramtype   : generic
 224     default     : 16384
 225
 226   ram_init_file:
 227     datatype    : file
 228     description : Initial on-chip RAM contents
 229     paramtype   : generic
 230
 231   reset_low:
 232     datatype    : bool
 233     description : External reset button polarity
 234     paramtype   : generic
 235
 236   clk_input:
 237     datatype    : int
 238     description : Clock input frequency in HZ (for top-generic based boards)
 239     paramtype   : generic
 240     default     : 100000000
 241
 242   clk_frequency:
 243     datatype    : int
 244     description : Generated system clock frequency in HZ (for top-generic based boards)
 245     paramtype   : generic
 246     default     : 100000000
 247
 248   disable_flatten_core:
 249     datatype    : bool
 250     description : Prevent Vivado from flattening the main core components
 251     paramtype   : generic
 252     default     : false
 253
 254   use_litedram:
 255     datatype    : bool
 256     description : Use liteDRAM
 257     paramtype   : generic
 258     default     : false