microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67
  68   debug_xilinx:
  69     files:
  70       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  71
  72   debug_dummy:
  73     files:
  74       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  75
  76   nexys_a7:
  77     files:
  78       - fpga/nexys_a7.xdc : {file_type : xdc}
  79       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  80       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  81
  82   nexys_video:
  83     files:
  84       - fpga/nexys-video.xdc : {file_type : xdc}
  85       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  86       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  87
  88   arty_a7:
  89     files:
  90       - fpga/arty_a7.xdc : {file_type : xdc}
  91       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  92       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  93
  94   cmod_a7-35:
  95     files:
  96       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  97       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  98       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  99
 100   litedram:
 101       depend : [":microwatt:litedram"]
 102
 103 targets:
 104   nexys_a7:
 105     default_tool: vivado
 106     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, xilinx_specific]
 107     parameters :
 108       - memory_size
 109       - ram_init_file
 110       - clk_input
 111       - clk_frequency
 112       - disable_flatten_core
 113       - log_length=2048
 114     tools:
 115       vivado: {part : xc7a100tcsg324-1}
 116     toplevel : toplevel
 117
 118   nexys_video-nodram:
 119     default_tool: vivado
 120     filesets: [core, nexys_video, soc, fpga, debug_xilinx, xilinx_specific]
 121     parameters :
 122       - memory_size
 123       - ram_init_file
 124       - clk_input
 125       - clk_frequency
 126       - disable_flatten_core
 127       - spi_flash_offset=10485760
 128       - log_length=2048
 129     tools:
 130       vivado: {part : xc7a200tsbg484-1}
 131     toplevel : toplevel
 132
 133   nexys_video:
 134     default_tool: vivado
 135     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, xilinx_specific]
 136     parameters:
 137       - memory_size
 138       - ram_init_file
 139       - use_litedram=true
 140       - disable_flatten_core
 141       - no_bram
 142       - spi_flash_offset=10485760
 143       - log_length=2048
 144     generate: [dram_nexys_video]
 145     tools:
 146       vivado: {part : xc7a200tsbg484-1}
 147     toplevel : toplevel
 148
 149   arty_a7-35-nodram:
 150     default_tool: vivado
 151     filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
 152     parameters :
 153       - memory_size
 154       - ram_init_file
 155       - clk_input
 156       - clk_frequency
 157       - disable_flatten_core
 158       - spi_flash_offset=3145728
 159       - log_length=512
 160     tools:
 161       vivado: {part : xc7a35ticsg324-1L}
 162     toplevel : toplevel
 163
 164   arty_a7-35:
 165     default_tool: vivado
 166     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, xilinx_specific]
 167     parameters :
 168       - memory_size
 169       - ram_init_file
 170       - use_litedram=true
 171       - disable_flatten_core
 172       - no_bram
 173       - spi_flash_offset=3145728
 174       - log_length=512
 175     generate: [dram_arty]
 176     tools:
 177       vivado: {part : xc7a35ticsg324-1L}
 178     toplevel : toplevel
 179
 180   arty_a7-100-nodram:
 181     default_tool: vivado
 182     filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
 183     parameters :
 184       - memory_size
 185       - ram_init_file
 186       - clk_input
 187       - clk_frequency
 188       - disable_flatten_core
 189       - spi_flash_offset=4194304
 190       - log_length=2048
 191     tools:
 192       vivado: {part : xc7a100ticsg324-1L}
 193     toplevel : toplevel
 194
 195   arty_a7-100:
 196     default_tool: vivado
 197     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, xilinx_specific]
 198     parameters:
 199       - memory_size
 200       - ram_init_file
 201       - use_litedram=true
 202       - disable_flatten_core
 203       - no_bram
 204       - spi_flash_offset=4194304
 205       - log_length=2048
 206     generate: [dram_arty]
 207     tools:
 208       vivado: {part : xc7a100ticsg324-1L}
 209     toplevel : toplevel
 210
 211   cmod_a7-35:
 212     default_tool: vivado
 213     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, xilinx_specific]
 214     parameters :
 215       - memory_size
 216       - ram_init_file
 217       - reset_low=false
 218       - clk_input=12000000
 219       - clk_frequency
 220       - disable_flatten_core
 221       - log_length=512
 222     tools:
 223       vivado: {part : xc7a35tcpg236-1}
 224     toplevel : toplevel
 225
 226   synth:
 227     filesets: [core, soc, xilinx_specific]
 228     tools:
 229       vivado: {pnr : none}
 230     toplevel: core
 231
 232 generate:
 233   dram_arty:
 234     generator: litedram_gen
 235     parameters: {board : arty}
 236
 237   dram_nexys_video:
 238     generator: litedram_gen
 239     parameters: {board : nexys-video}
 240
 241 parameters:
 242   memory_size:
 243     datatype    : int
 244     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 245     paramtype   : generic
 246     default     : 16384
 247
 248   ram_init_file:
 249     datatype    : file
 250     description : Initial on-chip RAM contents
 251     paramtype   : generic
 252
 253   reset_low:
 254     datatype    : bool
 255     description : External reset button polarity
 256     paramtype   : generic
 257
 258   clk_input:
 259     datatype    : int
 260     description : Clock input frequency in HZ (for top-generic based boards)
 261     paramtype   : generic
 262     default     : 100000000
 263
 264   clk_frequency:
 265     datatype    : int
 266     description : Generated system clock frequency in HZ (for top-generic based boards)
 267     paramtype   : generic
 268     default     : 100000000
 269
 270   disable_flatten_core:
 271     datatype    : bool
 272     description : Prevent Vivado from flattening the main core components
 273     paramtype   : generic
 274     default     : false
 275
 276   use_litedram:
 277     datatype    : bool
 278     description : Use liteDRAM
 279     paramtype   : generic
 280     default     : false
 281
 282   no_bram:
 283     datatype    : bool
 284     description : No internal block RAM (only DRAM and init code carrying payload)
 285     paramtype   : generic
 286     default     : false
 287
 288   spi_flash_offset:
 289     datatype    : int
 290     description : Offset (in bytes) in the SPI flash of the code payload to run
 291     paramtype   : generic
 292
 293   log_length:
 294     datatype    : int
 295     description : Length of the core log buffer in entries (32 bytes each)
 296     paramtype   : generic