microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67
  68   debug_xilinx:
  69     files:
  70       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  71
  72   debug_dummy:
  73     files:
  74       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  75
  76   nexys_a7:
  77     files:
  78       - fpga/nexys_a7.xdc : {file_type : xdc}
  79       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  80       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  81
  82   nexys_video:
  83     files:
  84       - fpga/nexys-video.xdc : {file_type : xdc}
  85       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  86       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  87
  88   acorn_cle_215:
  89     files:
  90       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  91       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  92       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  93
  94   genesys2:
  95     files:
  96       - fpga/genesys2.xdc : {file_type : xdc}
  97       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  98       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
  99
 100   arty_a7:
 101     files:
 102       - fpga/arty_a7.xdc : {file_type : xdc}
 103       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 104       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 105
 106   cmod_a7-35:
 107     files:
 108       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 109       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 110       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 111
 112   litedram:
 113       depend : [":microwatt:litedram"]
 114
 115   liteeth:
 116       depend : [":microwatt:liteeth"]
 117
 118   uart16550:
 119       depend : ["::uart16550"]
 120
 121 targets:
 122   nexys_a7:
 123     default_tool: vivado
 124     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 125     parameters :
 126       - memory_size
 127       - ram_init_file
 128       - clk_input
 129       - clk_frequency
 130       - disable_flatten_core
 131       - log_length=2048
 132       - uart_is_16550
 133     tools:
 134       vivado: {part : xc7a100tcsg324-1}
 135     toplevel : toplevel
 136
 137   acorn-cle-215-nodram:
 138     default_tool: vivado
 139     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 140     parameters :
 141       - memory_size
 142       - ram_init_file
 143       - clk_input
 144       - clk_frequency
 145       - disable_flatten_core
 146       - spi_flash_offset=10485760
 147       - log_length=2048
 148       - uart_is_16550
 149     tools:
 150       vivado: {part : xc7a200tsbg484-2}
 151     toplevel : toplevel
 152
 153   genesys2-nodram:
 154     default_tool: vivado
 155     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 156     parameters :
 157       - memory_size
 158       - ram_init_file
 159       - clk_frequency
 160       - use_litedram=false
 161       - no_bram=false
 162       - disable_flatten_core
 163       - spi_flash_offset=10485760
 164       - log_length=2048
 165       - uart_is_16550=false
 166     tools:
 167       vivado: {part : xc7k325tffg900-2}
 168     toplevel : toplevel
 169
 170   acorn-cle-215:
 171     default_tool: vivado
 172     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 173     parameters :
 174       - memory_size
 175       - ram_init_file
 176       - use_litedram=true
 177       - disable_flatten_core
 178       - no_bram
 179       - spi_flash_offset=10485760
 180       - log_length=2048
 181       - uart_is_16550
 182     generate: [litedram_acorn_cle_215]
 183     tools:
 184       vivado: {part : xc7a200tsbg484-2}
 185     toplevel : toplevel
 186
 187   genesys2:
 188     default_tool: vivado
 189     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 190     parameters :
 191       - memory_size
 192       - ram_init_file
 193       - use_litedram=true
 194       - disable_flatten_core
 195       - no_bram
 196       - spi_flash_offset=10485760
 197       - log_length=2048
 198       - uart_is_16550=false
 199     generate: [litedram_genesys2]
 200     tools:
 201       vivado: {part : xc7k325tffg900-2}
 202     toplevel : toplevel
 203
 204   nexys_video-nodram:
 205     default_tool: vivado
 206     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 207     parameters :
 208       - memory_size
 209       - ram_init_file
 210       - clk_input
 211       - clk_frequency
 212       - disable_flatten_core
 213       - spi_flash_offset=10485760
 214       - log_length=2048
 215       - uart_is_16550
 216     tools:
 217       vivado: {part : xc7a200tsbg484-1}
 218     toplevel : toplevel
 219
 220   nexys_video:
 221     default_tool: vivado
 222     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 223     parameters:
 224       - memory_size
 225       - ram_init_file
 226       - use_litedram=true
 227       - disable_flatten_core
 228       - no_bram
 229       - spi_flash_offset=10485760
 230       - log_length=2048
 231       - uart_is_16550
 232     generate: [litedram_nexys_video]
 233     tools:
 234       vivado: {part : xc7a200tsbg484-1}
 235     toplevel : toplevel
 236
 237   arty_a7-35-nodram:
 238     default_tool: vivado
 239     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 240     parameters :
 241       - memory_size
 242       - ram_init_file
 243       - clk_input
 244       - clk_frequency
 245       - disable_flatten_core
 246       - spi_flash_offset=3145728
 247       - log_length=512
 248       - uart_is_16550
 249       - has_uart1
 250     tools:
 251       vivado: {part : xc7a35ticsg324-1L}
 252     toplevel : toplevel
 253
 254   arty_a7-35:
 255     default_tool: vivado
 256     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 257     parameters :
 258       - memory_size
 259       - ram_init_file
 260       - use_litedram=true
 261       - use_liteeth=true
 262       - disable_flatten_core
 263       - no_bram
 264       - spi_flash_offset=3145728
 265       - log_length=512
 266       - uart_is_16550
 267       - has_uart1
 268     generate: [litedram_arty, liteeth_arty]
 269     tools:
 270       vivado: {part : xc7a35ticsg324-1L}
 271     toplevel : toplevel
 272
 273   arty_a7-100-nodram:
 274     default_tool: vivado
 275     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 276     parameters :
 277       - memory_size
 278       - ram_init_file
 279       - clk_input
 280       - clk_frequency
 281       - disable_flatten_core
 282       - spi_flash_offset=4194304
 283       - log_length=2048
 284       - uart_is_16550
 285       - has_uart1
 286     tools:
 287       vivado: {part : xc7a100ticsg324-1L}
 288     toplevel : toplevel
 289
 290   arty_a7-100:
 291     default_tool: vivado
 292     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 293     parameters:
 294       - memory_size
 295       - ram_init_file
 296       - use_litedram=true
 297       - use_liteeth=true
 298       - disable_flatten_core
 299       - no_bram
 300       - spi_flash_offset=4194304
 301       - log_length=2048
 302       - uart_is_16550
 303       - has_uart1
 304     generate: [litedram_arty, liteeth_arty]
 305     tools:
 306       vivado: {part : xc7a100ticsg324-1L}
 307     toplevel : toplevel
 308
 309   cmod_a7-35:
 310     default_tool: vivado
 311     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 312     parameters :
 313       - memory_size
 314       - ram_init_file
 315       - reset_low=false
 316       - clk_input=12000000
 317       - clk_frequency
 318       - disable_flatten_core
 319       - log_length=512
 320       - uart_is_16550
 321     tools:
 322       vivado: {part : xc7a35tcpg236-1}
 323     toplevel : toplevel
 324
 325   synth:
 326     filesets: [core, soc, xilinx_specific]
 327     tools:
 328       vivado: {pnr : none}
 329     toplevel: core
 330
 331 generate:
 332   litedram_arty:
 333     generator: litedram_gen
 334     parameters: {board : arty}
 335
 336   liteeth_arty:
 337     generator: liteeth_gen
 338     parameters: {board : arty}
 339
 340   litedram_nexys_video:
 341     generator: litedram_gen
 342     parameters: {board : nexys-video}
 343
 344   litedram_acorn_cle_215:
 345     generator: litedram_gen
 346     parameters: {board : acorn-cle-215}
 347
 348   litedram_genesys2:
 349     generator: litedram_gen
 350     parameters: {board : genesys2}
 351
 352 parameters:
 353   memory_size:
 354     datatype    : int
 355     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 356     paramtype   : generic
 357     default     : 16384
 358
 359   ram_init_file:
 360     datatype    : file
 361     description : Initial on-chip RAM contents
 362     paramtype   : generic
 363
 364   reset_low:
 365     datatype    : bool
 366     description : External reset button polarity
 367     paramtype   : generic
 368
 369   clk_input:
 370     datatype    : int
 371     description : Clock input frequency in HZ (for top-generic based boards)
 372     paramtype   : generic
 373     default     : 100000000
 374
 375   clk_frequency:
 376     datatype    : int
 377     description : Generated system clock frequency in HZ (for top-generic based boards)
 378     paramtype   : generic
 379     default     : 100000000
 380
 381   disable_flatten_core:
 382     datatype    : bool
 383     description : Prevent Vivado from flattening the main core components
 384     paramtype   : generic
 385     default     : false
 386
 387   use_litedram:
 388     datatype    : bool
 389     description : Use liteDRAM
 390     paramtype   : generic
 391     default     : false
 392
 393   use_liteeth:
 394     datatype    : bool
 395     description : Use liteEth
 396     paramtype   : generic
 397     default     : false
 398
 399   uart_is_16550:
 400     datatype    : bool
 401     description : Use 16550-compatible UART from OpenCores
 402     paramtype   : generic
 403     default     : true
 404
 405   has_uart1:
 406     datatype    : bool
 407     description : Enable second UART (always 16550-compatible)
 408     paramtype   : generic
 409     default     : false
 410
 411   no_bram:
 412     datatype    : bool
 413     description : No internal block RAM (only DRAM and init code carrying payload)
 414     paramtype   : generic
 415     default     : false
 416
 417   spi_flash_offset:
 418     datatype    : int
 419     description : Offset (in bytes) in the SPI flash of the code payload to run
 420     paramtype   : generic
 421
 422   log_length:
 423     datatype    : int
 424     description : Length of the core log buffer in entries (32 bytes each)
 425     paramtype   : generic