microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - dcache.vhdl
  29       - multiply.vhdl
  30       - divider.vhdl
  31       - rotator.vhdl
  32       - writeback.vhdl
  33       - insn_helpers.vhdl
  34       - core.vhdl
  35       - icache.vhdl
  36       - plru.vhdl
  37       - cache_ram.vhdl
  38       - core_debug.vhdl
  39       - utils.vhdl
  40     file_type : vhdlSource-2008
  41
  42   soc:
  43     files:
  44       - wishbone_arbiter.vhdl
  45       - wishbone_debug_master.vhdl
  46       - wishbone_bram_wrapper.vhdl
  47       - soc.vhdl
  48     file_type : vhdlSource-2008
  49
  50   fpga:
  51     files:
  52       - fpga/main_bram.vhdl
  53       - fpga/soc_reset.vhdl
  54       - fpga/pp_fifo.vhd
  55       - fpga/pp_soc_uart.vhd
  56       - fpga/pp_utilities.vhd
  57       - fpga/toplevel.vhdl
  58       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  59     file_type : vhdlSource-2008
  60
  61   debug_xilinx:
  62     files:
  63       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  64
  65   debug_dummy:
  66     files:
  67       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  68
  69   nexys_a7:
  70     files:
  71       - fpga/nexys_a7.xdc : {file_type : xdc}
  72       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  73
  74   nexys_video:
  75     files:
  76       - fpga/nexys-video.xdc : {file_type : xdc}
  77       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  78
  79   arty_a7:
  80     files:
  81       - fpga/arty_a7.xdc : {file_type : xdc}
  82       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  83
  84   cmod_a7-35:
  85     files:
  86       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  87       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  88
  89 targets:
  90   nexys_a7:
  91     default_tool: vivado
  92     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  93     parameters :
  94       - memory_size
  95       - ram_init_file
  96       - clk_input
  97       - clk_frequency
  98       - disable_flatten_core
  99     tools:
 100       vivado: {part : xc7a100tcsg324-1}
 101     toplevel : toplevel
 102
 103   nexys_video:
 104     default_tool: vivado
 105     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 106     parameters :
 107       - memory_size
 108       - ram_init_file
 109       - clk_input
 110       - clk_frequency
 111       - disable_flatten_core
 112     tools:
 113       vivado: {part : xc7a200tsbg484-1}
 114     toplevel : toplevel
 115
 116   arty_a7-35:
 117     default_tool: vivado
 118     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 119     parameters :
 120       - memory_size
 121       - ram_init_file
 122       - clk_input
 123       - clk_frequency
 124       - disable_flatten_core
 125     tools:
 126       vivado: {part : xc7a35ticsg324-1L}
 127     toplevel : toplevel
 128
 129   arty_a7-100:
 130     default_tool: vivado
 131     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 132     parameters :
 133       - memory_size
 134       - ram_init_file
 135       - clk_input
 136       - clk_frequency
 137       - disable_flatten_core
 138     tools:
 139       vivado: {part : xc7a100ticsg324-1L}
 140     toplevel : toplevel
 141
 142   cmod_a7-35:
 143     default_tool: vivado
 144     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 145     parameters :
 146       - memory_size
 147       - ram_init_file
 148       - reset_low=false
 149       - clk_input=12000000
 150       - clk_frequency
 151       - disable_flatten_core
 152     tools:
 153       vivado: {part : xc7a35tcpg236-1}
 154     toplevel : toplevel
 155
 156   synth:
 157     filesets: [core, soc]
 158     tools:
 159       vivado: {pnr : none}
 160     toplevel: core
 161
 162 parameters:
 163   memory_size:
 164     datatype    : int
 165     description : On-chip memory size (bytes)
 166     paramtype   : generic
 167     default     : 16384
 168
 169   ram_init_file:
 170     datatype    : file
 171     description : Initial on-chip RAM contents
 172     paramtype   : generic
 173
 174   reset_low:
 175     datatype    : bool
 176     description : External reset button polarity
 177     paramtype   : generic
 178
 179   clk_input:
 180     datatype    : int
 181     description : Clock input frequency in HZ (for top-generic based boards)
 182     paramtype   : generic
 183     default     : 100000000
 184
 185   clk_frequency:
 186     datatype    : int
 187     description : Generated system clock frequency in HZ (for top-generic based boards)
 188     paramtype   : generic
 189     default     : 50000000
 190
 191   disable_flatten_core:
 192     datatype    : bool
 193     description : Prevent Vivado from flattening the main core components
 194     paramtype   : generic
 195     default     : false