microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  68       - fpga/fpga-random.xdc : {file_type : xdc}
  69
  70   debug_xilinx:
  71     files:
  72       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  73
  74   debug_dummy:
  75     files:
  76       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  77
  78   nexys_a7:
  79     files:
  80       - fpga/nexys_a7.xdc : {file_type : xdc}
  81       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  82       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  83
  84   nexys_video:
  85     files:
  86       - fpga/nexys-video.xdc : {file_type : xdc}
  87       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  88       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  89
  90   acorn_cle_215:
  91     files:
  92       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  93       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  94       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  95
  96   genesys2:
  97     files:
  98       - fpga/genesys2.xdc : {file_type : xdc}
  99       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 100       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 101
 102   arty_a7:
 103     files:
 104       - fpga/arty_a7.xdc : {file_type : xdc}
 105       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 106       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 107
 108   cmod_a7-35:
 109     files:
 110       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 111       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 112       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 113
 114   litedram:
 115       depend : [":microwatt:litedram"]
 116
 117   liteeth:
 118       depend : [":microwatt:liteeth"]
 119
 120   uart16550:
 121       depend : ["::uart16550"]
 122
 123 targets:
 124   nexys_a7:
 125     default_tool: vivado
 126     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 127     parameters :
 128       - memory_size
 129       - ram_init_file
 130       - clk_input
 131       - clk_frequency
 132       - disable_flatten_core
 133       - log_length=2048
 134       - uart_is_16550
 135     tools:
 136       vivado: {part : xc7a100tcsg324-1}
 137     toplevel : toplevel
 138
 139   acorn-cle-215-nodram:
 140     default_tool: vivado
 141     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 142     parameters :
 143       - memory_size
 144       - ram_init_file
 145       - clk_input
 146       - clk_frequency
 147       - disable_flatten_core
 148       - spi_flash_offset=10485760
 149       - log_length=2048
 150       - uart_is_16550
 151     tools:
 152       vivado: {part : xc7a200tsbg484-2}
 153     toplevel : toplevel
 154
 155   genesys2-nodram:
 156     default_tool: vivado
 157     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 158     parameters :
 159       - memory_size
 160       - ram_init_file
 161       - clk_frequency
 162       - use_litedram=false
 163       - no_bram=false
 164       - disable_flatten_core
 165       - spi_flash_offset=10485760
 166       - log_length=2048
 167       - uart_is_16550=false
 168     tools:
 169       vivado: {part : xc7k325tffg900-2}
 170     toplevel : toplevel
 171
 172   acorn-cle-215:
 173     default_tool: vivado
 174     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 175     parameters :
 176       - memory_size
 177       - ram_init_file
 178       - use_litedram=true
 179       - disable_flatten_core
 180       - no_bram
 181       - spi_flash_offset=10485760
 182       - log_length=2048
 183       - uart_is_16550
 184     generate: [litedram_acorn_cle_215]
 185     tools:
 186       vivado: {part : xc7a200tsbg484-2}
 187     toplevel : toplevel
 188
 189   genesys2:
 190     default_tool: vivado
 191     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 192     parameters :
 193       - memory_size
 194       - ram_init_file
 195       - use_litedram=true
 196       - disable_flatten_core
 197       - no_bram
 198       - spi_flash_offset=10485760
 199       - log_length=2048
 200       - uart_is_16550=false
 201     generate: [litedram_genesys2]
 202     tools:
 203       vivado: {part : xc7k325tffg900-2}
 204     toplevel : toplevel
 205
 206   nexys_video-nodram:
 207     default_tool: vivado
 208     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 209     parameters :
 210       - memory_size
 211       - ram_init_file
 212       - clk_input
 213       - clk_frequency
 214       - disable_flatten_core
 215       - spi_flash_offset=10485760
 216       - log_length=2048
 217       - uart_is_16550
 218     tools:
 219       vivado: {part : xc7a200tsbg484-1}
 220     toplevel : toplevel
 221
 222   nexys_video:
 223     default_tool: vivado
 224     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 225     parameters:
 226       - memory_size
 227       - ram_init_file
 228       - use_litedram=true
 229       - disable_flatten_core
 230       - no_bram
 231       - spi_flash_offset=10485760
 232       - log_length=2048
 233       - uart_is_16550
 234     generate: [litedram_nexys_video]
 235     tools:
 236       vivado: {part : xc7a200tsbg484-1}
 237     toplevel : toplevel
 238
 239   arty_a7-35-nodram:
 240     default_tool: vivado
 241     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 242     parameters :
 243       - memory_size
 244       - ram_init_file
 245       - clk_input
 246       - clk_frequency
 247       - disable_flatten_core
 248       - spi_flash_offset=3145728
 249       - log_length=512
 250       - uart_is_16550
 251       - has_uart1
 252     tools:
 253       vivado: {part : xc7a35ticsg324-1L}
 254     toplevel : toplevel
 255
 256   arty_a7-35:
 257     default_tool: vivado
 258     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 259     parameters :
 260       - memory_size
 261       - ram_init_file
 262       - use_litedram=true
 263       - use_liteeth=true
 264       - disable_flatten_core
 265       - no_bram
 266       - spi_flash_offset=3145728
 267       - log_length=512
 268       - uart_is_16550
 269       - has_uart1
 270     generate: [litedram_arty, liteeth_arty]
 271     tools:
 272       vivado: {part : xc7a35ticsg324-1L}
 273     toplevel : toplevel
 274
 275   arty_a7-100-nodram:
 276     default_tool: vivado
 277     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 278     parameters :
 279       - memory_size
 280       - ram_init_file
 281       - clk_input
 282       - clk_frequency
 283       - disable_flatten_core
 284       - spi_flash_offset=4194304
 285       - log_length=2048
 286       - uart_is_16550
 287       - has_uart1
 288     tools:
 289       vivado: {part : xc7a100ticsg324-1L}
 290     toplevel : toplevel
 291
 292   arty_a7-100:
 293     default_tool: vivado
 294     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 295     parameters:
 296       - memory_size
 297       - ram_init_file
 298       - use_litedram=true
 299       - use_liteeth=true
 300       - disable_flatten_core
 301       - no_bram
 302       - spi_flash_offset=4194304
 303       - log_length=2048
 304       - uart_is_16550
 305       - has_uart1
 306     generate: [litedram_arty, liteeth_arty]
 307     tools:
 308       vivado: {part : xc7a100ticsg324-1L}
 309     toplevel : toplevel
 310
 311   cmod_a7-35:
 312     default_tool: vivado
 313     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 314     parameters :
 315       - memory_size
 316       - ram_init_file
 317       - reset_low=false
 318       - clk_input=12000000
 319       - clk_frequency
 320       - disable_flatten_core
 321       - log_length=512
 322       - uart_is_16550
 323     tools:
 324       vivado: {part : xc7a35tcpg236-1}
 325     toplevel : toplevel
 326
 327   synth:
 328     filesets: [core, soc, xilinx_specific]
 329     tools:
 330       vivado: {pnr : none}
 331     toplevel: core
 332
 333 generate:
 334   litedram_arty:
 335     generator: litedram_gen
 336     parameters: {board : arty}
 337
 338   liteeth_arty:
 339     generator: liteeth_gen
 340     parameters: {board : arty}
 341
 342   litedram_nexys_video:
 343     generator: litedram_gen
 344     parameters: {board : nexys-video}
 345
 346   litedram_acorn_cle_215:
 347     generator: litedram_gen
 348     parameters: {board : acorn-cle-215}
 349
 350   litedram_genesys2:
 351     generator: litedram_gen
 352     parameters: {board : genesys2}
 353
 354 parameters:
 355   memory_size:
 356     datatype    : int
 357     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 358     paramtype   : generic
 359     default     : 16384
 360
 361   ram_init_file:
 362     datatype    : file
 363     description : Initial on-chip RAM contents
 364     paramtype   : generic
 365
 366   reset_low:
 367     datatype    : bool
 368     description : External reset button polarity
 369     paramtype   : generic
 370
 371   clk_input:
 372     datatype    : int
 373     description : Clock input frequency in HZ (for top-generic based boards)
 374     paramtype   : generic
 375     default     : 100000000
 376
 377   clk_frequency:
 378     datatype    : int
 379     description : Generated system clock frequency in HZ (for top-generic based boards)
 380     paramtype   : generic
 381     default     : 100000000
 382
 383   disable_flatten_core:
 384     datatype    : bool
 385     description : Prevent Vivado from flattening the main core components
 386     paramtype   : generic
 387     default     : false
 388
 389   use_litedram:
 390     datatype    : bool
 391     description : Use liteDRAM
 392     paramtype   : generic
 393     default     : false
 394
 395   use_liteeth:
 396     datatype    : bool
 397     description : Use liteEth
 398     paramtype   : generic
 399     default     : false
 400
 401   uart_is_16550:
 402     datatype    : bool
 403     description : Use 16550-compatible UART from OpenCores
 404     paramtype   : generic
 405     default     : true
 406
 407   has_uart1:
 408     datatype    : bool
 409     description : Enable second UART (always 16550-compatible)
 410     paramtype   : generic
 411     default     : false
 412
 413   no_bram:
 414     datatype    : bool
 415     description : No internal block RAM (only DRAM and init code carrying payload)
 416     paramtype   : generic
 417     default     : false
 418
 419   spi_flash_offset:
 420     datatype    : int
 421     description : Offset (in bytes) in the SPI flash of the code payload to run
 422     paramtype   : generic
 423
 424   log_length:
 425     datatype    : int
 426     description : Length of the core log buffer in entries (32 bytes each)
 427     paramtype   : generic