microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67
  68   debug_xilinx:
  69     files:
  70       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  71
  72   debug_dummy:
  73     files:
  74       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  75
  76   nexys_a7:
  77     files:
  78       - fpga/nexys_a7.xdc : {file_type : xdc}
  79       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  80       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  81
  82   nexys_video:
  83     files:
  84       - fpga/nexys-video.xdc : {file_type : xdc}
  85       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  86       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  87
  88   arty_a7:
  89     files:
  90       - fpga/arty_a7.xdc : {file_type : xdc}
  91       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  92       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  93
  94   cmod_a7-35:
  95     files:
  96       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  97       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  98       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  99
 100   litedram:
 101       depend : [":microwatt:litedram"]
 102
 103   liteeth:
 104       depend : [":microwatt:liteeth"]
 105
 106   uart16550:
 107       depend : ["::uart16550"]
 108
 109 targets:
 110   nexys_a7:
 111     default_tool: vivado
 112     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 113     parameters :
 114       - memory_size
 115       - ram_init_file
 116       - clk_input
 117       - clk_frequency
 118       - disable_flatten_core
 119       - log_length=2048
 120       - uart_is_16550
 121       - has_uart1
 122     tools:
 123       vivado: {part : xc7a100tcsg324-1}
 124     toplevel : toplevel
 125
 126   nexys_video-nodram:
 127     default_tool: vivado
 128     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 129     parameters :
 130       - memory_size
 131       - ram_init_file
 132       - clk_input
 133       - clk_frequency
 134       - disable_flatten_core
 135       - spi_flash_offset=10485760
 136       - log_length=2048
 137       - uart_is_16550
 138       - has_uart1
 139     tools:
 140       vivado: {part : xc7a200tsbg484-1}
 141     toplevel : toplevel
 142
 143   nexys_video:
 144     default_tool: vivado
 145     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 146     parameters:
 147       - memory_size
 148       - ram_init_file
 149       - use_litedram=true
 150       - disable_flatten_core
 151       - no_bram
 152       - spi_flash_offset=10485760
 153       - log_length=2048
 154     generate: [litedram_nexys_video]
 155     tools:
 156       vivado: {part : xc7a200tsbg484-1}
 157     toplevel : toplevel
 158
 159   arty_a7-35-nodram:
 160     default_tool: vivado
 161     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 162     parameters :
 163       - memory_size
 164       - ram_init_file
 165       - clk_input
 166       - clk_frequency
 167       - disable_flatten_core
 168       - spi_flash_offset=3145728
 169       - log_length=512
 170       - uart_is_16550
 171       - has_uart1
 172     tools:
 173       vivado: {part : xc7a35ticsg324-1L}
 174     toplevel : toplevel
 175
 176   arty_a7-35:
 177     default_tool: vivado
 178     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 179     parameters :
 180       - memory_size
 181       - ram_init_file
 182       - use_litedram=true
 183       - use_liteeth=true
 184       - disable_flatten_core
 185       - no_bram
 186       - spi_flash_offset=3145728
 187       - log_length=512
 188       - uart_is_16550
 189       - has_uart1
 190     generate: [litedram_arty, liteeth_arty]
 191     tools:
 192       vivado: {part : xc7a35ticsg324-1L}
 193     toplevel : toplevel
 194
 195   arty_a7-100-nodram:
 196     default_tool: vivado
 197     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 198     parameters :
 199       - memory_size
 200       - ram_init_file
 201       - clk_input
 202       - clk_frequency
 203       - disable_flatten_core
 204       - spi_flash_offset=4194304
 205       - log_length=2048
 206       - uart_is_16550
 207       - has_uart1
 208     tools:
 209       vivado: {part : xc7a100ticsg324-1L}
 210     toplevel : toplevel
 211
 212   arty_a7-100:
 213     default_tool: vivado
 214     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 215     parameters:
 216       - memory_size
 217       - ram_init_file
 218       - use_litedram=true
 219       - use_liteeth=true
 220       - disable_flatten_core
 221       - no_bram
 222       - spi_flash_offset=4194304
 223       - log_length=2048
 224       - uart_is_16550
 225       - has_uart1
 226     generate: [litedram_arty, liteeth_arty]
 227     tools:
 228       vivado: {part : xc7a100ticsg324-1L}
 229     toplevel : toplevel
 230
 231   cmod_a7-35:
 232     default_tool: vivado
 233     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 234     parameters :
 235       - memory_size
 236       - ram_init_file
 237       - reset_low=false
 238       - clk_input=12000000
 239       - clk_frequency
 240       - disable_flatten_core
 241       - log_length=512
 242       - uart_is_16550
 243       - has_uart1
 244     tools:
 245       vivado: {part : xc7a35tcpg236-1}
 246     toplevel : toplevel
 247
 248   synth:
 249     filesets: [core, soc, xilinx_specific]
 250     tools:
 251       vivado: {pnr : none}
 252     toplevel: core
 253
 254 generate:
 255   litedram_arty:
 256     generator: litedram_gen
 257     parameters: {board : arty}
 258
 259   liteeth_arty:
 260     generator: liteeth_gen
 261     parameters: {board : arty}
 262
 263   litedram_nexys_video:
 264     generator: litedram_gen
 265     parameters: {board : nexys-video}
 266
 267 parameters:
 268   memory_size:
 269     datatype    : int
 270     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 271     paramtype   : generic
 272     default     : 16384
 273
 274   ram_init_file:
 275     datatype    : file
 276     description : Initial on-chip RAM contents
 277     paramtype   : generic
 278
 279   reset_low:
 280     datatype    : bool
 281     description : External reset button polarity
 282     paramtype   : generic
 283
 284   clk_input:
 285     datatype    : int
 286     description : Clock input frequency in HZ (for top-generic based boards)
 287     paramtype   : generic
 288     default     : 100000000
 289
 290   clk_frequency:
 291     datatype    : int
 292     description : Generated system clock frequency in HZ (for top-generic based boards)
 293     paramtype   : generic
 294     default     : 100000000
 295
 296   disable_flatten_core:
 297     datatype    : bool
 298     description : Prevent Vivado from flattening the main core components
 299     paramtype   : generic
 300     default     : false
 301
 302   use_litedram:
 303     datatype    : bool
 304     description : Use liteDRAM
 305     paramtype   : generic
 306     default     : false
 307
 308   use_liteeth:
 309     datatype    : bool
 310     description : Use liteEth
 311     paramtype   : generic
 312     default     : false
 313
 314   uart_is_16550:
 315     datatype    : bool
 316     description : Use 16550-compatible UART from OpenCores
 317     paramtype   : generic
 318     default     : false
 319
 320   has_uart1:
 321     datatype    : bool
 322     description : Enable second UART (always 16550-compatible)
 323     paramtype   : generic
 324     default     : false
 325
 326   no_bram:
 327     datatype    : bool
 328     description : No internal block RAM (only DRAM and init code carrying payload)
 329     paramtype   : generic
 330     default     : false
 331
 332   spi_flash_offset:
 333     datatype    : int
 334     description : Offset (in bytes) in the SPI flash of the code payload to run
 335     paramtype   : generic
 336
 337   log_length:
 338     datatype    : int
 339     description : Length of the core log buffer in entries (32 bytes each)
 340     paramtype   : generic