microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - multiply.vhdl
  31       - divider.vhdl
  32       - rotator.vhdl
  33       - writeback.vhdl
  34       - insn_helpers.vhdl
  35       - core.vhdl
  36       - icache.vhdl
  37       - plru.vhdl
  38       - cache_ram.vhdl
  39       - core_debug.vhdl
  40       - utils.vhdl
  41     file_type : vhdlSource-2008
  42
  43   soc:
  44     files:
  45       - wishbone_arbiter.vhdl
  46       - wishbone_debug_master.vhdl
  47       - wishbone_bram_wrapper.vhdl
  48       - soc.vhdl
  49     file_type : vhdlSource-2008
  50
  51   fpga:
  52     files:
  53       - fpga/main_bram.vhdl
  54       - fpga/soc_reset.vhdl
  55       - fpga/pp_fifo.vhd
  56       - fpga/pp_soc_uart.vhd
  57       - fpga/pp_utilities.vhd
  58       - fpga/toplevel.vhdl
  59       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  60     file_type : vhdlSource-2008
  61
  62   debug_xilinx:
  63     files:
  64       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  65
  66   debug_dummy:
  67     files:
  68       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  69
  70   nexys_a7:
  71     files:
  72       - fpga/nexys_a7.xdc : {file_type : xdc}
  73       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  74
  75   nexys_video:
  76     files:
  77       - fpga/nexys-video.xdc : {file_type : xdc}
  78       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  79
  80   arty_a7:
  81     files:
  82       - fpga/arty_a7.xdc : {file_type : xdc}
  83       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  84
  85   cmod_a7-35:
  86     files:
  87       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  88       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  89
  90 targets:
  91   nexys_a7:
  92     default_tool: vivado
  93     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  94     parameters :
  95       - memory_size
  96       - ram_init_file
  97       - clk_input
  98       - clk_frequency
  99       - disable_flatten_core
 100     tools:
 101       vivado: {part : xc7a100tcsg324-1}
 102     toplevel : toplevel
 103
 104   nexys_video:
 105     default_tool: vivado
 106     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 107     parameters :
 108       - memory_size
 109       - ram_init_file
 110       - clk_input
 111       - clk_frequency
 112       - disable_flatten_core
 113     tools:
 114       vivado: {part : xc7a200tsbg484-1}
 115     toplevel : toplevel
 116
 117   arty_a7-35:
 118     default_tool: vivado
 119     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 120     parameters :
 121       - memory_size
 122       - ram_init_file
 123       - clk_input
 124       - clk_frequency
 125       - disable_flatten_core
 126     tools:
 127       vivado: {part : xc7a35ticsg324-1L}
 128     toplevel : toplevel
 129
 130   arty_a7-100:
 131     default_tool: vivado
 132     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 133     parameters :
 134       - memory_size
 135       - ram_init_file
 136       - clk_input
 137       - clk_frequency
 138       - disable_flatten_core
 139     tools:
 140       vivado: {part : xc7a100ticsg324-1L}
 141     toplevel : toplevel
 142
 143   cmod_a7-35:
 144     default_tool: vivado
 145     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 146     parameters :
 147       - memory_size
 148       - ram_init_file
 149       - reset_low=false
 150       - clk_input=12000000
 151       - clk_frequency
 152       - disable_flatten_core
 153     tools:
 154       vivado: {part : xc7a35tcpg236-1}
 155     toplevel : toplevel
 156
 157   synth:
 158     filesets: [core, soc]
 159     tools:
 160       vivado: {pnr : none}
 161     toplevel: core
 162
 163 parameters:
 164   memory_size:
 165     datatype    : int
 166     description : On-chip memory size (bytes)
 167     paramtype   : generic
 168     default     : 16384
 169
 170   ram_init_file:
 171     datatype    : file
 172     description : Initial on-chip RAM contents
 173     paramtype   : generic
 174
 175   reset_low:
 176     datatype    : bool
 177     description : External reset button polarity
 178     paramtype   : generic
 179
 180   clk_input:
 181     datatype    : int
 182     description : Clock input frequency in HZ (for top-generic based boards)
 183     paramtype   : generic
 184     default     : 100000000
 185
 186   clk_frequency:
 187     datatype    : int
 188     description : Generated system clock frequency in HZ (for top-generic based boards)
 189     paramtype   : generic
 190     default     : 50000000
 191
 192   disable_flatten_core:
 193     datatype    : bool
 194     description : Prevent Vivado from flattening the main core components
 195     paramtype   : generic
 196     default     : false