microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - execute1.vhdl
  22       - execute2.vhdl
  23       - loadstore1.vhdl
  24       - loadstore2.vhdl
  25       - multiply.vhdl
  26       - divider.vhdl
  27       - writeback.vhdl
  28       - insn_helpers.vhdl
  29       - wishbone_debug_master.vhdl
  30       - core.vhdl
  31       - icache.vhdl
  32       - core_debug.vhdl
  33     file_type : vhdlSource-2008
  34
  35   soc:
  36     files:
  37       - wishbone_arbiter.vhdl
  38       - wishbone_debug_master.vhdl
  39       - soc.vhdl
  40     file_type : vhdlSource-2008
  41
  42   fpga:
  43     files:
  44       - fpga/pp_fifo.vhd
  45       - fpga/mw_soc_memory.vhdl
  46       - fpga/soc_reset.vhdl
  47       - fpga/pp_soc_uart.vhd
  48       - fpga/pp_utilities.vhd
  49       - fpga/toplevel.vhdl
  50       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  51     file_type : vhdlSource-2008
  52
  53   debug_xilinx:
  54     files:
  55       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  56
  57   debug_dummy:
  58     files:
  59       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  60
  61   nexys_a7:
  62     files:
  63       - fpga/nexys_a7.xdc : {file_type : xdc}
  64       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  65
  66   nexys_video:
  67     files:
  68       - fpga/nexys-video.xdc : {file_type : xdc}
  69       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  70
  71   arty_a7:
  72     files:
  73       - fpga/arty_a7.xdc : {file_type : xdc}
  74       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  75
  76   cmod_a7-35:
  77     files:
  78       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  79       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  80
  81 targets:
  82   nexys_a7:
  83     default_tool: vivado
  84     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  85     parameters : [memory_size, ram_init_file]
  86     tools:
  87       vivado: {part : xc7a100tcsg324-1}
  88     toplevel : toplevel
  89
  90   nexys_video:
  91     default_tool: vivado
  92     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
  93     parameters : [memory_size, ram_init_file]
  94     tools:
  95       vivado: {part : xc7a200tsbg484-1}
  96     toplevel : toplevel
  97
  98   arty_a7-35:
  99     default_tool: vivado
 100     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 101     parameters : [memory_size, ram_init_file]
 102     tools:
 103       vivado: {part : xc7a35ticsg324-1L}
 104     toplevel : toplevel
 105
 106   arty_a7-100:
 107     default_tool: vivado
 108     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 109     parameters : [memory_size, ram_init_file]
 110     tools:
 111       vivado: {part : xc7a100ticsg324-1L}
 112     toplevel : toplevel
 113
 114   cmod_a7-35:
 115     default_tool: vivado
 116     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 117     parameters : [memory_size, ram_init_file, reset_low=false]
 118     tools:
 119       vivado: {part : xc7a35tcpg236-1}
 120     toplevel : toplevel
 121
 122   synth:
 123     filesets: [core, soc]
 124     tools:
 125       vivado: {pnr : none}
 126     toplevel: core
 127
 128 parameters:
 129   memory_size:
 130     datatype    : int
 131     description : On-chip memory size (bytes)
 132     paramtype   : generic
 133
 134   ram_init_file:
 135     datatype    : file
 136     description : Initial on-chip RAM contents
 137     paramtype   : generic
 138
 139   reset_low:
 140     datatype    : bool
 141     description : External reset button polarity
 142     paramtype   : generic