microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - dcache.vhdl
  29       - multiply.vhdl
  30       - divider.vhdl
  31       - rotator.vhdl
  32       - writeback.vhdl
  33       - insn_helpers.vhdl
  34       - core.vhdl
  35       - icache.vhdl
  36       - plru.vhdl
  37       - cache_ram.vhdl
  38       - core_debug.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - soc.vhdl
  46     file_type : vhdlSource-2008
  47
  48   fpga:
  49     files:
  50       - fpga/pp_fifo.vhd
  51       - fpga/mw_soc_memory.vhdl
  52       - fpga/soc_reset.vhdl
  53       - fpga/pp_soc_uart.vhd
  54       - fpga/pp_utilities.vhd
  55       - fpga/toplevel.vhdl
  56       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  57     file_type : vhdlSource-2008
  58
  59   debug_xilinx:
  60     files:
  61       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  62
  63   debug_dummy:
  64     files:
  65       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  66
  67   nexys_a7:
  68     files:
  69       - fpga/nexys_a7.xdc : {file_type : xdc}
  70       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  71
  72   nexys_video:
  73     files:
  74       - fpga/nexys-video.xdc : {file_type : xdc}
  75       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  76
  77   arty_a7:
  78     files:
  79       - fpga/arty_a7.xdc : {file_type : xdc}
  80       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  81
  82   cmod_a7-35:
  83     files:
  84       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  85       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  86
  87 targets:
  88   nexys_a7:
  89     default_tool: vivado
  90     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  91     parameters :
  92       - memory_size
  93       - ram_init_file
  94       - clk_input
  95       - clk_frequency
  96     tools:
  97       vivado: {part : xc7a100tcsg324-1}
  98     toplevel : toplevel
  99
 100   nexys_video:
 101     default_tool: vivado
 102     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 103     parameters :
 104       - memory_size
 105       - ram_init_file
 106       - clk_input
 107       - clk_frequency
 108     tools:
 109       vivado: {part : xc7a200tsbg484-1}
 110     toplevel : toplevel
 111
 112   arty_a7-35:
 113     default_tool: vivado
 114     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 115     parameters :
 116       - memory_size
 117       - ram_init_file
 118       - clk_input
 119       - clk_frequency
 120     tools:
 121       vivado: {part : xc7a35ticsg324-1L}
 122     toplevel : toplevel
 123
 124   arty_a7-100:
 125     default_tool: vivado
 126     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 127     parameters :
 128       - memory_size
 129       - ram_init_file
 130       - clk_input
 131       - clk_frequency
 132     tools:
 133       vivado: {part : xc7a100ticsg324-1L}
 134     toplevel : toplevel
 135
 136   cmod_a7-35:
 137     default_tool: vivado
 138     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 139     parameters :
 140       - memory_size
 141       - ram_init_file
 142       - reset_low=false
 143       - clk_input=12000000
 144       - clk_frequency
 145     tools:
 146       vivado: {part : xc7a35tcpg236-1}
 147     toplevel : toplevel
 148
 149   synth:
 150     filesets: [core, soc]
 151     tools:
 152       vivado: {pnr : none}
 153     toplevel: core
 154
 155 parameters:
 156   memory_size:
 157     datatype    : int
 158     description : On-chip memory size (bytes)
 159     paramtype   : generic
 160
 161   ram_init_file:
 162     datatype    : file
 163     description : Initial on-chip RAM contents
 164     paramtype   : generic
 165
 166   reset_low:
 167     datatype    : bool
 168     description : External reset button polarity
 169     paramtype   : generic
 170
 171   clk_input:
 172     datatype    : int
 173     description : Clock input frequency in HZ (for top-generic based boards)
 174     paramtype   : generic
 175     default     : 100000000
 176
 177   clk_frequency:
 178     datatype    : int
 179     description : Generated system clock frequency in HZ (for top-generic based boards)
 180     paramtype   : generic
 181     default     : 50000000