microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - execute1.vhdl
  23       - execute2.vhdl
  24       - loadstore1.vhdl
  25       - loadstore2.vhdl
  26       - multiply.vhdl
  27       - divider.vhdl
  28       - rotator.vhdl
  29       - writeback.vhdl
  30       - insn_helpers.vhdl
  31       - core.vhdl
  32       - icache.vhdl
  33       - core_debug.vhdl
  34     file_type : vhdlSource-2008
  35
  36   soc:
  37     files:
  38       - wishbone_arbiter.vhdl
  39       - wishbone_debug_master.vhdl
  40       - soc.vhdl
  41     file_type : vhdlSource-2008
  42
  43   fpga:
  44     files:
  45       - fpga/pp_fifo.vhd
  46       - fpga/mw_soc_memory.vhdl
  47       - fpga/soc_reset.vhdl
  48       - fpga/pp_soc_uart.vhd
  49       - fpga/pp_utilities.vhd
  50       - fpga/toplevel.vhdl
  51       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  52     file_type : vhdlSource-2008
  53
  54   debug_xilinx:
  55     files:
  56       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  57
  58   debug_dummy:
  59     files:
  60       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  61
  62   nexys_a7:
  63     files:
  64       - fpga/nexys_a7.xdc : {file_type : xdc}
  65       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  66
  67   nexys_video:
  68     files:
  69       - fpga/nexys-video.xdc : {file_type : xdc}
  70       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  71
  72   arty_a7:
  73     files:
  74       - fpga/arty_a7.xdc : {file_type : xdc}
  75       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  76
  77   cmod_a7-35:
  78     files:
  79       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  80       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  81
  82 targets:
  83   nexys_a7:
  84     default_tool: vivado
  85     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  86     parameters :
  87       - memory_size
  88       - ram_init_file
  89       - clk_input
  90       - clk_frequency
  91     tools:
  92       vivado: {part : xc7a100tcsg324-1}
  93     toplevel : toplevel
  94
  95   nexys_video:
  96     default_tool: vivado
  97     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
  98     parameters :
  99       - memory_size
 100       - ram_init_file
 101       - clk_input
 102       - clk_frequency
 103     tools:
 104       vivado: {part : xc7a200tsbg484-1}
 105     toplevel : toplevel
 106
 107   arty_a7-35:
 108     default_tool: vivado
 109     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 110     parameters :
 111       - memory_size
 112       - ram_init_file
 113       - clk_input
 114       - clk_frequency
 115     tools:
 116       vivado: {part : xc7a35ticsg324-1L}
 117     toplevel : toplevel
 118
 119   arty_a7-100:
 120     default_tool: vivado
 121     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 122     parameters :
 123       - memory_size
 124       - ram_init_file
 125       - clk_input
 126       - clk_frequency
 127     tools:
 128       vivado: {part : xc7a100ticsg324-1L}
 129     toplevel : toplevel
 130
 131   cmod_a7-35:
 132     default_tool: vivado
 133     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 134     parameters :
 135       - memory_size
 136       - ram_init_file
 137       - reset_low=false
 138       - clk_input=12000000
 139     tools:
 140       vivado: {part : xc7a35tcpg236-1}
 141     toplevel : toplevel
 142
 143   synth:
 144     filesets: [core, soc]
 145     tools:
 146       vivado: {pnr : none}
 147     toplevel: core
 148
 149 parameters:
 150   memory_size:
 151     datatype    : int
 152     description : On-chip memory size (bytes)
 153     paramtype   : generic
 154
 155   ram_init_file:
 156     datatype    : file
 157     description : Initial on-chip RAM contents
 158     paramtype   : generic
 159
 160   reset_low:
 161     datatype    : bool
 162     description : External reset button polarity
 163     paramtype   : generic
 164
 165   clk_input:
 166     datatype    : int
 167     description : Clock input frequency in HZ (for top-generic based boards)
 168     paramtype   : generic
 169     default     : 100000000
 170
 171   clk_frequency:
 172     datatype    : int
 173     description : Generated system clock frequency in HZ (for top-generic based boards)
 174     paramtype   : generic
 175     default     : 50000000