microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - multiply.vhdl
  31       - divider.vhdl
  32       - rotator.vhdl
  33       - writeback.vhdl
  34       - insn_helpers.vhdl
  35       - core.vhdl
  36       - icache.vhdl
  37       - plru.vhdl
  38       - cache_ram.vhdl
  39       - core_debug.vhdl
  40       - utils.vhdl
  41     file_type : vhdlSource-2008
  42
  43   soc:
  44     files:
  45       - wishbone_arbiter.vhdl
  46       - wishbone_debug_master.vhdl
  47       - wishbone_bram_wrapper.vhdl
  48       - soc.vhdl
  49       - xics.vhdl
  50       - syscon.vhdl
  51     file_type : vhdlSource-2008
  52
  53   fpga:
  54     files:
  55       - fpga/main_bram.vhdl
  56       - fpga/soc_reset.vhdl
  57       - fpga/pp_fifo.vhd
  58       - fpga/pp_soc_uart.vhd
  59       - fpga/pp_utilities.vhd
  60       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  61     file_type : vhdlSource-2008
  62
  63   debug_xilinx:
  64     files:
  65       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  66
  67   debug_dummy:
  68     files:
  69       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  70
  71   nexys_a7:
  72     files:
  73       - fpga/nexys_a7.xdc : {file_type : xdc}
  74       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  75       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  76
  77   nexys_video:
  78     files:
  79       - fpga/nexys-video.xdc : {file_type : xdc}
  80       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  81       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  82
  83   arty_a7:
  84     files:
  85       - fpga/arty_a7.xdc : {file_type : xdc}
  86       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  87       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  88
  89   cmod_a7-35:
  90     files:
  91       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  92       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  93       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  94
  95   litedram:
  96       depend : [":microwatt:litedram"]
  97
  98 targets:
  99   nexys_a7:
 100     default_tool: vivado
 101     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
 102     parameters :
 103       - memory_size
 104       - ram_init_file
 105       - clk_input
 106       - clk_frequency
 107       - disable_flatten_core
 108     tools:
 109       vivado: {part : xc7a100tcsg324-1}
 110     toplevel : toplevel
 111
 112   nexys_video-nodram:
 113     default_tool: vivado
 114     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 115     parameters :
 116       - memory_size
 117       - ram_init_file
 118       - clk_input
 119       - clk_frequency
 120       - disable_flatten_core
 121     tools:
 122       vivado: {part : xc7a200tsbg484-1}
 123     toplevel : toplevel
 124
 125   nexys_video:
 126     default_tool: vivado
 127     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
 128     parameters:
 129       - memory_size
 130       - ram_init_file
 131       - use_litedram=true
 132       - disable_flatten_core
 133       - no_bram
 134     generate: [dram_nexys_video]
 135     tools:
 136       vivado: {part : xc7a200tsbg484-1}
 137     toplevel : toplevel
 138
 139   arty_a7-35-nodram:
 140     default_tool: vivado
 141     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 142     parameters :
 143       - memory_size
 144       - ram_init_file
 145       - clk_input
 146       - clk_frequency
 147       - disable_flatten_core
 148     tools:
 149       vivado: {part : xc7a35ticsg324-1L}
 150     toplevel : toplevel
 151
 152   arty_a7-35:
 153     default_tool: vivado
 154     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 155     parameters :
 156       - memory_size
 157       - ram_init_file
 158       - use_litedram=true
 159       - disable_flatten_core
 160       - no_bram
 161     generate: [dram_arty]
 162     tools:
 163       vivado: {part : xc7a35ticsg324-1L}
 164     toplevel : toplevel
 165
 166   arty_a7-100-nodram:
 167     default_tool: vivado
 168     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 169     parameters :
 170       - memory_size
 171       - ram_init_file
 172       - clk_input
 173       - clk_frequency
 174       - disable_flatten_core
 175     tools:
 176       vivado: {part : xc7a100ticsg324-1L}
 177     toplevel : toplevel
 178
 179   arty_a7-100:
 180     default_tool: vivado
 181     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 182     parameters:
 183       - memory_size
 184       - ram_init_file
 185       - use_litedram=true
 186       - disable_flatten_core
 187       - no_bram
 188     generate: [dram_arty]
 189     tools:
 190       vivado: {part : xc7a100ticsg324-1L}
 191     toplevel : toplevel
 192
 193   cmod_a7-35:
 194     default_tool: vivado
 195     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 196     parameters :
 197       - memory_size
 198       - ram_init_file
 199       - reset_low=false
 200       - clk_input=12000000
 201       - clk_frequency
 202       - disable_flatten_core
 203     tools:
 204       vivado: {part : xc7a35tcpg236-1}
 205     toplevel : toplevel
 206
 207   synth:
 208     filesets: [core, soc]
 209     tools:
 210       vivado: {pnr : none}
 211     toplevel: core
 212
 213 generate:
 214   dram_arty:
 215     generator: litedram_gen
 216     parameters: {board : arty}
 217
 218   dram_nexys_video:
 219     generator: litedram_gen
 220     parameters: {board : nexys-video}
 221
 222 parameters:
 223   memory_size:
 224     datatype    : int
 225     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 226     paramtype   : generic
 227     default     : 16384
 228
 229   ram_init_file:
 230     datatype    : file
 231     description : Initial on-chip RAM contents
 232     paramtype   : generic
 233
 234   reset_low:
 235     datatype    : bool
 236     description : External reset button polarity
 237     paramtype   : generic
 238
 239   clk_input:
 240     datatype    : int
 241     description : Clock input frequency in HZ (for top-generic based boards)
 242     paramtype   : generic
 243     default     : 100000000
 244
 245   clk_frequency:
 246     datatype    : int
 247     description : Generated system clock frequency in HZ (for top-generic based boards)
 248     paramtype   : generic
 249     default     : 100000000
 250
 251   disable_flatten_core:
 252     datatype    : bool
 253     description : Prevent Vivado from flattening the main core components
 254     paramtype   : generic
 255     default     : false
 256
 257   use_litedram:
 258     datatype    : bool
 259     description : Use liteDRAM
 260     paramtype   : generic
 261     default     : false
 262
 263   no_bram:
 264     datatype    : bool
 265     description : No internal block RAM (only DRAM and init code carrying payload)
 266     paramtype   : generic
 267     default     : false