Pass wishbone record to bram memory module
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - execute1.vhdl
22 - execute2.vhdl
23 - loadstore1.vhdl
24 - loadstore2.vhdl
25 - multiply.vhdl
26 - writeback.vhdl
27 - wishbone_arbiter.vhdl
28 - insn_helpers.vhdl
29 - core.vhdl
30 file_type : vhdlSource-2008
31
32 soc:
33 files:
34 - fpga/pp_fifo.vhd
35 - fpga/mw_soc_memory.vhdl
36 - fpga/soc_reset.vhdl
37 - fpga/pp_soc_uart.vhd
38 - fpga/pp_utilities.vhd
39 - fpga/soc.vhdl
40 - fpga/toplevel.vhdl
41 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
42 file_type : vhdlSource-2008
43
44 nexys_a7:
45 files:
46 - fpga/nexys_a7.xdc : {file_type : xdc}
47 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
48
49 nexys_video:
50 files:
51 - fpga/nexys-video.xdc : {file_type : xdc}
52 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
53
54 arty_a7-35:
55 files:
56 - fpga/arty_a7-35.xdc : {file_type : xdc}
57 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
58
59 cmod_a7-35:
60 files:
61 - fpga/cmod_a7-35.xdc : {file_type : xdc}
62 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
63
64 targets:
65 nexys_a7:
66 default_tool: vivado
67 filesets: [core, nexys_a7, soc]
68 parameters : [memory_size, ram_init_file]
69 tools:
70 vivado: {part : xc7a100tcsg324-1}
71 toplevel : toplevel
72
73 nexys_video:
74 default_tool: vivado
75 filesets: [core, nexys_video, soc]
76 parameters : [memory_size, ram_init_file]
77 tools:
78 vivado: {part : xc7a200tsbg484-1}
79 toplevel : toplevel
80
81 arty_a7-35:
82 default_tool: vivado
83 filesets: [core, arty_a7-35, soc]
84 parameters : [memory_size, ram_init_file]
85 tools:
86 vivado: {part : xc7a35ticsg324-1L}
87 toplevel : toplevel
88
89 cmod_a7-35:
90 default_tool: vivado
91 filesets: [core, cmod_a7-35, soc]
92 parameters : [memory_size, ram_init_file, reset_low=false]
93 tools:
94 vivado: {part : xc7a35tcpg236-1}
95 toplevel : toplevel
96
97 synth:
98 filesets: [core]
99 tools:
100 vivado: {pnr : none}
101 toplevel: core
102
103 parameters:
104 memory_size:
105 datatype : int
106 description : On-chip memory size (bytes)
107 paramtype : generic
108
109 ram_init_file:
110 datatype : file
111 description : Initial on-chip RAM contents
112 paramtype : generic
113
114 reset_low:
115 datatype : bool
116 description : External reset button polarity
117 paramtype : generic