Add a divider unit and a testbench for it
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - execute1.vhdl
22 - execute2.vhdl
23 - loadstore1.vhdl
24 - loadstore2.vhdl
25 - multiply.vhdl
26 - divider.vhdl
27 - writeback.vhdl
28 - insn_helpers.vhdl
29 - core.vhdl
30 - icache.vhdl
31 file_type : vhdlSource-2008
32
33 soc:
34 files:
35 - wishbone_arbiter.vhdl
36 - soc.vhdl
37 file_type : vhdlSource-2008
38
39 fpga:
40 files:
41 - fpga/pp_fifo.vhd
42 - fpga/mw_soc_memory.vhdl
43 - fpga/soc_reset.vhdl
44 - fpga/pp_soc_uart.vhd
45 - fpga/pp_utilities.vhd
46 - fpga/toplevel.vhdl
47 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
48 file_type : vhdlSource-2008
49
50 nexys_a7:
51 files:
52 - fpga/nexys_a7.xdc : {file_type : xdc}
53 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
54
55 nexys_video:
56 files:
57 - fpga/nexys-video.xdc : {file_type : xdc}
58 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
59
60 arty_a7-35:
61 files:
62 - fpga/arty_a7-35.xdc : {file_type : xdc}
63 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
64
65 cmod_a7-35:
66 files:
67 - fpga/cmod_a7-35.xdc : {file_type : xdc}
68 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
69
70 targets:
71 nexys_a7:
72 default_tool: vivado
73 filesets: [core, nexys_a7, soc, fpga]
74 parameters : [memory_size, ram_init_file]
75 tools:
76 vivado: {part : xc7a100tcsg324-1}
77 toplevel : toplevel
78
79 nexys_video:
80 default_tool: vivado
81 filesets: [core, nexys_video, soc, fpga]
82 parameters : [memory_size, ram_init_file]
83 tools:
84 vivado: {part : xc7a200tsbg484-1}
85 toplevel : toplevel
86
87 arty_a7-35:
88 default_tool: vivado
89 filesets: [core, arty_a7-35, soc, fpga]
90 parameters : [memory_size, ram_init_file]
91 tools:
92 vivado: {part : xc7a35ticsg324-1L}
93 toplevel : toplevel
94
95 cmod_a7-35:
96 default_tool: vivado
97 filesets: [core, cmod_a7-35, soc, fpga]
98 parameters : [memory_size, ram_init_file, reset_low=false]
99 tools:
100 vivado: {part : xc7a35tcpg236-1}
101 toplevel : toplevel
102
103 synth:
104 filesets: [core, soc]
105 tools:
106 vivado: {pnr : none}
107 toplevel: core
108
109 parameters:
110 memory_size:
111 datatype : int
112 description : On-chip memory size (bytes)
113 paramtype : generic
114
115 ram_init_file:
116 datatype : file
117 description : Initial on-chip RAM contents
118 paramtype : generic
119
120 reset_low:
121 datatype : bool
122 description : External reset button polarity
123 paramtype : generic