microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - control.vhdl
  24       - execute1.vhdl
  25       - execute2.vhdl
  26       - loadstore1.vhdl
  27       - loadstore2.vhdl
  28       - multiply.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38     file_type : vhdlSource-2008
  39
  40   soc:
  41     files:
  42       - wishbone_arbiter.vhdl
  43       - wishbone_debug_master.vhdl
  44       - soc.vhdl
  45     file_type : vhdlSource-2008
  46
  47   fpga:
  48     files:
  49       - fpga/pp_fifo.vhd
  50       - fpga/mw_soc_memory.vhdl
  51       - fpga/soc_reset.vhdl
  52       - fpga/pp_soc_uart.vhd
  53       - fpga/pp_utilities.vhd
  54       - fpga/toplevel.vhdl
  55       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  56     file_type : vhdlSource-2008
  57
  58   debug_xilinx:
  59     files:
  60       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  61
  62   debug_dummy:
  63     files:
  64       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  65
  66   nexys_a7:
  67     files:
  68       - fpga/nexys_a7.xdc : {file_type : xdc}
  69       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  70
  71   nexys_video:
  72     files:
  73       - fpga/nexys-video.xdc : {file_type : xdc}
  74       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  75
  76   arty_a7:
  77     files:
  78       - fpga/arty_a7.xdc : {file_type : xdc}
  79       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  80
  81   cmod_a7-35:
  82     files:
  83       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  84       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  85
  86 targets:
  87   nexys_a7:
  88     default_tool: vivado
  89     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  90     parameters :
  91       - memory_size
  92       - ram_init_file
  93       - clk_input
  94       - clk_frequency
  95     tools:
  96       vivado: {part : xc7a100tcsg324-1}
  97     toplevel : toplevel
  98
  99   nexys_video:
 100     default_tool: vivado
 101     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 102     parameters :
 103       - memory_size
 104       - ram_init_file
 105       - clk_input
 106       - clk_frequency
 107     tools:
 108       vivado: {part : xc7a200tsbg484-1}
 109     toplevel : toplevel
 110
 111   arty_a7-35:
 112     default_tool: vivado
 113     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 114     parameters :
 115       - memory_size
 116       - ram_init_file
 117       - clk_input
 118       - clk_frequency
 119     tools:
 120       vivado: {part : xc7a35ticsg324-1L}
 121     toplevel : toplevel
 122
 123   arty_a7-100:
 124     default_tool: vivado
 125     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 126     parameters :
 127       - memory_size
 128       - ram_init_file
 129       - clk_input
 130       - clk_frequency
 131     tools:
 132       vivado: {part : xc7a100ticsg324-1L}
 133     toplevel : toplevel
 134
 135   cmod_a7-35:
 136     default_tool: vivado
 137     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 138     parameters :
 139       - memory_size
 140       - ram_init_file
 141       - reset_low=false
 142       - clk_input=12000000
 143       - clk_frequency
 144     tools:
 145       vivado: {part : xc7a35tcpg236-1}
 146     toplevel : toplevel
 147
 148   synth:
 149     filesets: [core, soc]
 150     tools:
 151       vivado: {pnr : none}
 152     toplevel: core
 153
 154 parameters:
 155   memory_size:
 156     datatype    : int
 157     description : On-chip memory size (bytes)
 158     paramtype   : generic
 159
 160   ram_init_file:
 161     datatype    : file
 162     description : Initial on-chip RAM contents
 163     paramtype   : generic
 164
 165   reset_low:
 166     datatype    : bool
 167     description : External reset button polarity
 168     paramtype   : generic
 169
 170   clk_input:
 171     datatype    : int
 172     description : Clock input frequency in HZ (for top-generic based boards)
 173     paramtype   : generic
 174     default     : 100000000
 175
 176   clk_frequency:
 177     datatype    : int
 178     description : Generated system clock frequency in HZ (for top-generic based boards)
 179     paramtype   : generic
 180     default     : 50000000