microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - execute1.vhdl
  24       - execute2.vhdl
  25       - loadstore1.vhdl
  26       - loadstore2.vhdl
  27       - multiply.vhdl
  28       - divider.vhdl
  29       - rotator.vhdl
  30       - writeback.vhdl
  31       - insn_helpers.vhdl
  32       - core.vhdl
  33       - icache.vhdl
  34       - plru.vhdl
  35       - cache_ram.vhdl
  36       - core_debug.vhdl
  37     file_type : vhdlSource-2008
  38
  39   soc:
  40     files:
  41       - wishbone_arbiter.vhdl
  42       - wishbone_debug_master.vhdl
  43       - soc.vhdl
  44     file_type : vhdlSource-2008
  45
  46   fpga:
  47     files:
  48       - fpga/pp_fifo.vhd
  49       - fpga/mw_soc_memory.vhdl
  50       - fpga/soc_reset.vhdl
  51       - fpga/pp_soc_uart.vhd
  52       - fpga/pp_utilities.vhd
  53       - fpga/toplevel.vhdl
  54       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  55     file_type : vhdlSource-2008
  56
  57   debug_xilinx:
  58     files:
  59       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  60
  61   debug_dummy:
  62     files:
  63       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  64
  65   nexys_a7:
  66     files:
  67       - fpga/nexys_a7.xdc : {file_type : xdc}
  68       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  69
  70   nexys_video:
  71     files:
  72       - fpga/nexys-video.xdc : {file_type : xdc}
  73       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  74
  75   arty_a7:
  76     files:
  77       - fpga/arty_a7.xdc : {file_type : xdc}
  78       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  79
  80   cmod_a7-35:
  81     files:
  82       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  83       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  84
  85 targets:
  86   nexys_a7:
  87     default_tool: vivado
  88     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  89     parameters :
  90       - memory_size
  91       - ram_init_file
  92       - clk_input
  93       - clk_frequency
  94     tools:
  95       vivado: {part : xc7a100tcsg324-1}
  96     toplevel : toplevel
  97
  98   nexys_video:
  99     default_tool: vivado
 100     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 101     parameters :
 102       - memory_size
 103       - ram_init_file
 104       - clk_input
 105       - clk_frequency
 106     tools:
 107       vivado: {part : xc7a200tsbg484-1}
 108     toplevel : toplevel
 109
 110   arty_a7-35:
 111     default_tool: vivado
 112     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 113     parameters :
 114       - memory_size
 115       - ram_init_file
 116       - clk_input
 117       - clk_frequency
 118     tools:
 119       vivado: {part : xc7a35ticsg324-1L}
 120     toplevel : toplevel
 121
 122   arty_a7-100:
 123     default_tool: vivado
 124     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 125     parameters :
 126       - memory_size
 127       - ram_init_file
 128       - clk_input
 129       - clk_frequency
 130     tools:
 131       vivado: {part : xc7a100ticsg324-1L}
 132     toplevel : toplevel
 133
 134   cmod_a7-35:
 135     default_tool: vivado
 136     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 137     parameters :
 138       - memory_size
 139       - ram_init_file
 140       - reset_low=false
 141       - clk_input=12000000
 142     tools:
 143       vivado: {part : xc7a35tcpg236-1}
 144     toplevel : toplevel
 145
 146   synth:
 147     filesets: [core, soc]
 148     tools:
 149       vivado: {pnr : none}
 150     toplevel: core
 151
 152 parameters:
 153   memory_size:
 154     datatype    : int
 155     description : On-chip memory size (bytes)
 156     paramtype   : generic
 157
 158   ram_init_file:
 159     datatype    : file
 160     description : Initial on-chip RAM contents
 161     paramtype   : generic
 162
 163   reset_low:
 164     datatype    : bool
 165     description : External reset button polarity
 166     paramtype   : generic
 167
 168   clk_input:
 169     datatype    : int
 170     description : Clock input frequency in HZ (for top-generic based boards)
 171     paramtype   : generic
 172     default     : 100000000
 173
 174   clk_frequency:
 175     datatype    : int
 176     description : Generated system clock frequency in HZ (for top-generic based boards)
 177     paramtype   : generic
 178     default     : 50000000