29 - wishbone_debug_master.vhdl
33 file_type : vhdlSource-2008
37 - wishbone_arbiter.vhdl
38 - wishbone_debug_master.vhdl
40 file_type : vhdlSource-2008
45 - fpga/mw_soc_memory.vhdl
47 - fpga/pp_soc_uart.vhd
48 - fpga/pp_utilities.vhd
50 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
51 file_type : vhdlSource-2008
55 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
59 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
63 - fpga/nexys_a7.xdc : {file_type : xdc}
64 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
68 - fpga/nexys-video.xdc : {file_type : xdc}
69 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
73 - fpga/arty_a7-35.xdc : {file_type : xdc}
74 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
78 - fpga/arty_a7-35.xdc : {file_type : xdc}
79 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
83 - fpga/cmod_a7-35.xdc : {file_type : xdc}
84 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
89 filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
90 parameters : [memory_size, ram_init_file]
92 vivado: {part : xc7a100tcsg324-1}
97 filesets: [core, nexys_video, soc, fpga, debug_xilinx]
98 parameters : [memory_size, ram_init_file]
100 vivado: {part : xc7a200tsbg484-1}
105 filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
106 parameters : [memory_size, ram_init_file]
108 vivado: {part : xc7a35ticsg324-1L}
113 filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
114 parameters : [memory_size, ram_init_file]
116 vivado: {part : xc7a100ticsg324-1L}
121 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
122 parameters : [memory_size, ram_init_file, reset_low=false]
124 vivado: {part : xc7a35tcpg236-1}
128 filesets: [core, soc]
136 description : On-chip memory size (bytes)
141 description : Initial on-chip RAM contents
146 description : External reset button polarity