Merge pull request #75 from paulusmack/master
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - execute1.vhdl
22 - execute2.vhdl
23 - loadstore1.vhdl
24 - loadstore2.vhdl
25 - multiply.vhdl
26 - divider.vhdl
27 - writeback.vhdl
28 - insn_helpers.vhdl
29 - wishbone_debug_master.vhdl
30 - core.vhdl
31 - icache.vhdl
32 - core_debug.vhdl
33 file_type : vhdlSource-2008
34
35 soc:
36 files:
37 - wishbone_arbiter.vhdl
38 - wishbone_debug_master.vhdl
39 - soc.vhdl
40 file_type : vhdlSource-2008
41
42 fpga:
43 files:
44 - fpga/pp_fifo.vhd
45 - fpga/mw_soc_memory.vhdl
46 - fpga/soc_reset.vhdl
47 - fpga/pp_soc_uart.vhd
48 - fpga/pp_utilities.vhd
49 - fpga/toplevel.vhdl
50 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
51 file_type : vhdlSource-2008
52
53 debug_xilinx:
54 files:
55 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
56
57 debug_dummy:
58 files:
59 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
60
61 nexys_a7:
62 files:
63 - fpga/nexys_a7.xdc : {file_type : xdc}
64 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
65
66 nexys_video:
67 files:
68 - fpga/nexys-video.xdc : {file_type : xdc}
69 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
70
71 arty_a7-35:
72 files:
73 - fpga/arty_a7-35.xdc : {file_type : xdc}
74 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
75
76 arty_a7-100:
77 files:
78 - fpga/arty_a7-35.xdc : {file_type : xdc}
79 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
80
81 cmod_a7-35:
82 files:
83 - fpga/cmod_a7-35.xdc : {file_type : xdc}
84 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
85
86 targets:
87 nexys_a7:
88 default_tool: vivado
89 filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
90 parameters : [memory_size, ram_init_file]
91 tools:
92 vivado: {part : xc7a100tcsg324-1}
93 toplevel : toplevel
94
95 nexys_video:
96 default_tool: vivado
97 filesets: [core, nexys_video, soc, fpga, debug_xilinx]
98 parameters : [memory_size, ram_init_file]
99 tools:
100 vivado: {part : xc7a200tsbg484-1}
101 toplevel : toplevel
102
103 arty_a7-35:
104 default_tool: vivado
105 filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
106 parameters : [memory_size, ram_init_file]
107 tools:
108 vivado: {part : xc7a35ticsg324-1L}
109 toplevel : toplevel
110
111 arty_a7-100:
112 default_tool: vivado
113 filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
114 parameters : [memory_size, ram_init_file]
115 tools:
116 vivado: {part : xc7a100ticsg324-1L}
117 toplevel : toplevel
118
119 cmod_a7-35:
120 default_tool: vivado
121 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
122 parameters : [memory_size, ram_init_file, reset_low=false]
123 tools:
124 vivado: {part : xc7a35tcpg236-1}
125 toplevel : toplevel
126
127 synth:
128 filesets: [core, soc]
129 tools:
130 vivado: {pnr : none}
131 toplevel: core
132
133 parameters:
134 memory_size:
135 datatype : int
136 description : On-chip memory size (bytes)
137 paramtype : generic
138
139 ram_init_file:
140 datatype : file
141 description : Initial on-chip RAM contents
142 paramtype : generic
143
144 reset_low:
145 datatype : bool
146 description : External reset button polarity
147 paramtype : generic