2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 -- Supports 4-level trees as in arch 3.0B, but not the two-step translation for
10 -- guests under a hypervisor (i.e. there is no gRA -> hRA translation).
17 l_in : in Loadstore1ToMmuType;
18 l_out : out MmuToLoadstore1Type;
20 d_out : out MmuToDcacheType;
21 d_in : in DcacheToMmuType;
23 i_out : out MmuToIcacheType
27 architecture behave of mmu is
29 type state_t is (IDLE,
41 type reg_stage_t is record
42 -- latched request from loadstore1
47 addr : std_ulogic_vector(63 downto 0);
48 inval_all : std_ulogic;
50 prtbl : std_ulogic_vector(63 downto 0);
51 pid : std_ulogic_vector(31 downto 0);
55 pgtbl0 : std_ulogic_vector(63 downto 0);
56 pt0_valid : std_ulogic;
57 pgtbl3 : std_ulogic_vector(63 downto 0);
58 pt3_valid : std_ulogic;
59 shift : unsigned(5 downto 0);
60 mask_size : unsigned(4 downto 0);
61 pgbase : std_ulogic_vector(55 downto 0);
62 pde : std_ulogic_vector(63 downto 0);
65 segerror : std_ulogic;
66 perm_err : std_ulogic;
67 rc_error : std_ulogic;
70 signal r, rin : reg_stage_t;
72 signal addrsh : std_ulogic_vector(15 downto 0);
73 signal mask : std_ulogic_vector(15 downto 0);
74 signal finalmask : std_ulogic_vector(43 downto 0);
77 -- Multiplex internal SPR values back to loadstore1, selected
79 l_out.sprval <= r.prtbl when l_in.sprn(9) = '1' else x"00000000" & r.pid;
83 if rising_edge(clk) then
89 r.prtbl <= (others => '0');
91 if rin.valid = '1' then
92 report "MMU got tlb miss for " & to_hstring(rin.addr);
94 if l_out.done = '1' then
95 report "MMU completing op with invalid=" & std_ulogic'image(l_out.invalid) &
96 " badtree=" & std_ulogic'image(l_out.badtree);
98 if rin.state = RADIX_LOOKUP then
99 report "radix lookup shift=" & integer'image(to_integer(rin.shift)) &
100 " msize=" & integer'image(to_integer(rin.mask_size));
102 if r.state = RADIX_LOOKUP then
103 report "send load addr=" & to_hstring(d_out.addr) &
104 " addrsh=" & to_hstring(addrsh) & " mask=" & to_hstring(mask);
111 -- Shift address bits 61--12 right by 0--47 bits and
112 -- supply the least significant 16 bits of the result.
113 addrshifter: process(all)
114 variable sh1 : std_ulogic_vector(30 downto 0);
115 variable sh2 : std_ulogic_vector(18 downto 0);
116 variable result : std_ulogic_vector(15 downto 0);
118 case r.shift(5 downto 4) is
120 sh1 := r.addr(42 downto 12);
122 sh1 := r.addr(58 downto 28);
124 sh1 := "0000000000000" & r.addr(61 downto 44);
126 case r.shift(3 downto 2) is
128 sh2 := sh1(18 downto 0);
130 sh2 := sh1(22 downto 4);
132 sh2 := sh1(26 downto 8);
134 sh2 := sh1(30 downto 12);
136 case r.shift(1 downto 0) is
138 result := sh2(15 downto 0);
140 result := sh2(16 downto 1);
142 result := sh2(17 downto 2);
144 result := sh2(18 downto 3);
149 -- generate mask for extracting address fields for PTE address generation
150 addrmaskgen: process(all)
151 variable m : std_ulogic_vector(15 downto 0);
153 -- mask_count has to be >= 5
155 for i in 5 to 15 loop
156 if i < to_integer(r.mask_size) then
163 -- generate mask for extracting address bits to go in TLB entry
164 -- in order to support pages > 4kB
165 finalmaskgen: process(all)
166 variable m : std_ulogic_vector(43 downto 0);
168 m := (others => '0');
169 for i in 0 to 43 loop
170 if i < to_integer(r.shift) then
178 variable v : reg_stage_t;
179 variable dcreq : std_ulogic;
180 variable tlb_load : std_ulogic;
181 variable itlb_load : std_ulogic;
182 variable tlbie_req : std_ulogic;
183 variable prtbl_rd : std_ulogic;
184 variable pt_valid : std_ulogic;
185 variable effpid : std_ulogic_vector(31 downto 0);
186 variable prtable_addr : std_ulogic_vector(63 downto 0);
187 variable rts : unsigned(5 downto 0);
188 variable mbits : unsigned(5 downto 0);
189 variable pgtable_addr : std_ulogic_vector(63 downto 0);
190 variable pte : std_ulogic_vector(63 downto 0);
191 variable tlb_data : std_ulogic_vector(63 downto 0);
192 variable nonzero : std_ulogic;
193 variable pgtbl : std_ulogic_vector(63 downto 0);
194 variable perm_ok : std_ulogic;
195 variable rc_ok : std_ulogic;
196 variable addr : std_ulogic_vector(63 downto 0);
197 variable data : std_ulogic_vector(63 downto 0);
214 -- Radix tree data structures in memory are big-endian,
215 -- so we need to byte-swap them
217 data(i * 8 + 7 downto i * 8) := d_in.data((7 - i) * 8 + 7 downto (7 - i) * 8);
222 if l_in.addr(63) = '0' then
224 pt_valid := r.pt0_valid;
227 pt_valid := r.pt3_valid;
229 -- rts == radix tree size, # address bits being translated
230 rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
231 -- mbits == # address bits to index top level of tree
232 mbits := unsigned('0' & pgtbl(4 downto 0));
233 -- set v.shift to rts so that we can use finalmask for the segment check
235 v.mask_size := mbits(4 downto 0);
236 v.pgbase := pgtbl(55 downto 8) & x"00";
238 if l_in.valid = '1' then
240 v.iside := l_in.iside;
241 v.store := not (l_in.load or l_in.iside);
243 if l_in.tlbie = '1' then
244 -- Invalidate all iTLB/dTLB entries for tlbie with
245 -- RB[IS] != 0 or RB[AP] != 0, or for slbia
246 v.inval_all := l_in.slbia or l_in.addr(11) or l_in.addr(10) or
247 l_in.addr(7) or l_in.addr(6) or l_in.addr(5);
248 -- The RIC field of the tlbie instruction comes across on the
249 -- sprn bus as bits 2--3. RIC=2 flushes process table caches.
250 if l_in.sprn(3) = '1' then
257 if pt_valid = '0' then
258 -- need to fetch process table entry
259 -- set v.shift so we can use finalmask for generating
260 -- the process table entry address
261 v.shift := unsigned('0' & r.prtbl(4 downto 0));
262 v.state := PROC_TBL_READ;
264 -- Use RPDS = 0 to disable radix tree walks
265 v.state := RADIX_FINISH;
268 v.state := SEGMENT_CHECK;
272 if l_in.mtspr = '1' then
273 -- Move to PID needs to invalidate L1 TLBs and cached
274 -- pgtbl0 value. Move to PRTBL does that plus
275 -- invalidating the cached pgtbl3 value as well.
276 if l_in.sprn(9) = '0' then
277 v.pid := l_in.rs(31 downto 0);
293 if d_in.done = '1' then
294 v.state := RADIX_FINISH;
297 when PROC_TBL_READ =>
300 v.state := PROC_TBL_WAIT;
302 when PROC_TBL_WAIT =>
303 if d_in.done = '1' then
304 if r.addr(63) = '1' then
311 -- rts == radix tree size, # address bits being translated
312 rts := unsigned('0' & data(62 downto 61) & data(7 downto 5));
313 -- mbits == # address bits to index top level of tree
314 mbits := unsigned('0' & data(4 downto 0));
315 -- set v.shift to rts so that we can use finalmask for the segment check
317 v.mask_size := mbits(4 downto 0);
318 v.pgbase := data(55 downto 8) & x"00";
320 v.state := RADIX_FINISH;
323 v.state := SEGMENT_CHECK;
326 if d_in.err = '1' then
327 v.state := RADIX_FINISH;
331 when SEGMENT_CHECK =>
332 mbits := '0' & r.mask_size;
333 v.shift := r.shift + (31 - 12) - mbits;
334 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
335 if r.addr(63) /= r.addr(62) or nonzero = '1' then
336 v.state := RADIX_FINISH;
338 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
339 v.state := RADIX_FINISH;
342 v.state := RADIX_LOOKUP;
347 v.state := RADIX_READ_WAIT;
349 when RADIX_READ_WAIT =>
350 if d_in.done = '1' then
353 if data(63) = '1' then
355 if data(62) = '1' then
356 -- check permissions and RC bits
358 if r.priv = '1' or data(3) = '0' then
359 if r.iside = '0' then
360 perm_ok := data(1) or (data(2) and not r.store);
362 -- no IAMR, so no KUEP support for now
363 -- deny execute permission if cache inhibited
364 perm_ok := data(0) and not data(5);
367 rc_ok := data(8) and (data(7) or not r.store);
368 if perm_ok = '1' and rc_ok = '1' then
369 v.state := RADIX_LOAD_TLB;
371 v.state := RADIX_FINISH;
372 v.perm_err := not perm_ok;
373 -- permission error takes precedence over RC error
374 v.rc_error := perm_ok;
377 mbits := unsigned('0' & data(4 downto 0));
378 if mbits < 5 or mbits > 16 or mbits > r.shift then
379 v.state := RADIX_FINISH;
382 v.shift := v.shift - mbits;
383 v.mask_size := mbits(4 downto 0);
384 v.pgbase := data(55 downto 8) & x"00";
385 v.state := RADIX_LOOKUP;
389 -- non-present PTE, generate a DSI
390 v.state := RADIX_FINISH;
394 if d_in.err = '1' then
395 v.state := RADIX_FINISH;
399 when RADIX_LOAD_TLB =>
401 if r.iside = '0' then
414 if v.state = RADIX_FINISH or (v.state = RADIX_LOAD_TLB and r.iside = '1') then
418 if r.addr(63) = '1' then
419 effpid := x"00000000";
423 prtable_addr := x"00" & r.prtbl(55 downto 36) &
424 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
425 (effpid(31 downto 8) and finalmask(23 downto 0))) &
426 effpid(7 downto 0) & "0000";
428 pgtable_addr := x"00" & r.pgbase(55 downto 19) &
429 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
432 ((r.pde(55 downto 12) and not finalmask) or (r.addr(55 downto 12) and finalmask))
433 & r.pde(11 downto 0);
439 if tlbie_req = '1' then
441 tlb_data := (others => '0');
442 elsif tlb_load = '1' then
443 addr := r.addr(63 downto 12) & x"000";
445 elsif prtbl_rd = '1' then
446 addr := prtable_addr;
447 tlb_data := (others => '0');
449 addr := pgtable_addr;
450 tlb_data := (others => '0');
453 l_out.done <= r.done;
454 l_out.invalid <= r.invalid;
455 l_out.badtree <= r.badtree;
456 l_out.segerr <= r.segerror;
457 l_out.perm_error <= r.perm_err;
458 l_out.rc_error <= r.rc_error;
460 d_out.valid <= dcreq;
461 d_out.tlbie <= tlbie_req;
462 d_out.doall <= r.inval_all;
463 d_out.tlbld <= tlb_load;
465 d_out.pte <= tlb_data;
467 i_out.tlbld <= itlb_load;
468 i_out.tlbie <= tlbie_req;
469 i_out.doall <= r.inval_all;
471 i_out.pte <= tlb_data;