multiply-32s.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 -- Signed 33b x 33b multiplier giving 64-bit product, with no addend,
   9 -- with fixed 1-cycle latency.
  10
  11 entity multiply_32s is
  12     port (
  13         clk   : in std_logic;
  14         stall : in std_ulogic;
  15
  16         m_in  : in MultiplyInputType;
  17         m_out : out MultiplyOutputType
  18         );
  19 end entity multiply_32s;
  20
  21 architecture behaviour of multiply_32s is
  22     type reg_type is record
  23         valid     : std_ulogic;
  24         data      : signed(65 downto 0);
  25     end record;
  26     constant reg_type_init : reg_type := (valid => '0', data => (others => '0'));
  27
  28     signal r, rin : reg_type := reg_type_init;
  29 begin
  30     multiply_0: process(clk)
  31     begin
  32         if rising_edge(clk) and stall = '0' then
  33             r <= rin;
  34         end if;
  35     end process;
  36
  37     multiply_1: process(all)
  38         variable v : reg_type;
  39         variable d : std_ulogic_vector(63 downto 0);
  40         variable ov : std_ulogic;
  41     begin
  42         v.valid := m_in.valid;
  43         v.data := signed((m_in.is_signed and m_in.data1(31)) & m_in.data1(31 downto 0)) *
  44                   signed((m_in.is_signed and m_in.data2(31)) & m_in.data2(31 downto 0));
  45
  46         d := std_ulogic_vector(r.data(63 downto 0));
  47
  48         ov := (or d(63 downto 31)) and not (and d(63 downto 31));
  49
  50         m_out.result <= 64x"0" & d;
  51         m_out.overflow <= ov;
  52         m_out.valid <= r.valid;
  53
  54         rin <= v;
  55     end process;
  56 end architecture behaviour;