multiply.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8
   9 entity multiply is
  10     generic (
  11         PIPELINE_DEPTH : natural := 16
  12         );
  13     port (
  14         clk   : in std_logic;
  15
  16         m_in  : in Decode2ToMultiplyType;
  17         m_out : out MultiplyToWritebackType
  18         );
  19 end entity multiply;
  20
  21 architecture behaviour of multiply is
  22     signal m: Decode2ToMultiplyType;
  23
  24     type multiply_pipeline_stage is record
  25         valid     : std_ulogic;
  26         insn_type  : insn_type_t;
  27         data      : signed(129 downto 0);
  28         write_reg : std_ulogic_vector(4 downto 0);
  29         rc        : std_ulogic;
  30     end record;
  31     constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0'));
  32
  33     type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
  34     constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
  35
  36     type reg_type is record
  37         multiply_pipeline : multiply_pipeline_type;
  38     end record;
  39
  40     signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
  41 begin
  42     multiply_0: process(clk)
  43     begin
  44         if rising_edge(clk) then
  45             m <= m_in;
  46             r <= rin;
  47         end if;
  48     end process;
  49
  50     multiply_1: process(all)
  51         variable v : reg_type;
  52         variable d : std_ulogic_vector(129 downto 0);
  53         variable d2 : std_ulogic_vector(63 downto 0);
  54     begin
  55         v := r;
  56
  57         m_out <= MultiplyToWritebackInit;
  58
  59         v.multiply_pipeline(0).valid := m.valid;
  60         v.multiply_pipeline(0).insn_type := m.insn_type;
  61         v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
  62         v.multiply_pipeline(0).write_reg := m.write_reg;
  63         v.multiply_pipeline(0).rc := m.rc;
  64
  65         loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
  66             v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
  67         end loop;
  68
  69         d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
  70
  71         case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
  72             when OP_MUL_L64 =>
  73                 d2 := d(63 downto 0);
  74             when OP_MUL_H32 =>
  75                 d2 := d(63 downto 32) & d(63 downto 32);
  76             when OP_MUL_H64 =>
  77                 d2 := d(127 downto 64);
  78             when others =>
  79                 --report "Illegal insn type in multiplier";
  80                 d2 := (others => '0');
  81         end case;
  82
  83         m_out.write_reg_data <= d2;
  84         m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
  85
  86         if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
  87             m_out.valid <= '1';
  88             m_out.write_reg_enable <= '1';
  89             m_out.rc <= v.multiply_pipeline(PIPELINE_DEPTH-1).rc;
  90         end if;
  91
  92         rin <= v;
  93     end process;
  94 end architecture behaviour;