multiply.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8 use work.ppc_fx_insns.all;
   9 use work.crhelpers.all;
  10
  11 entity multiply is
  12     generic (
  13         PIPELINE_DEPTH : natural := 2
  14         );
  15     port (
  16         clk   : in std_logic;
  17
  18         m_in  : in Decode2ToMultiplyType;
  19         m_out : out MultiplyToWritebackType
  20         );
  21 end entity multiply;
  22
  23 architecture behaviour of multiply is
  24     signal m: Decode2ToMultiplyType;
  25
  26     type multiply_pipeline_stage is record
  27         valid     : std_ulogic;
  28         insn_type  : insn_type_t;
  29         data      : signed(129 downto 0);
  30         write_reg : std_ulogic_vector(4 downto 0);
  31         rc        : std_ulogic;
  32     end record;
  33     constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0'));
  34
  35     type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
  36     constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
  37
  38     type reg_type is record
  39         multiply_pipeline : multiply_pipeline_type;
  40     end record;
  41
  42     signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
  43 begin
  44     multiply_0: process(clk)
  45     begin
  46         if rising_edge(clk) then
  47             m <= m_in;
  48             r <= rin;
  49         end if;
  50     end process;
  51
  52     multiply_1: process(all)
  53         variable v : reg_type;
  54         variable d : std_ulogic_vector(129 downto 0);
  55         variable d2 : std_ulogic_vector(63 downto 0);
  56     begin
  57         v := r;
  58
  59         m_out <= MultiplyToWritebackInit;
  60
  61         v.multiply_pipeline(0).valid := m.valid;
  62         v.multiply_pipeline(0).insn_type := m.insn_type;
  63         v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
  64         v.multiply_pipeline(0).write_reg := m.write_reg;
  65         v.multiply_pipeline(0).rc := m.rc;
  66
  67         loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
  68             v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
  69         end loop;
  70
  71         d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
  72
  73         case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
  74             when OP_MUL_L64 =>
  75                 d2 := d(63 downto 0);
  76             when OP_MUL_H32 =>
  77                 d2 := d(63 downto 32) & d(63 downto 32);
  78             when OP_MUL_H64 =>
  79                 d2 := d(127 downto 64);
  80             when others =>
  81                 --report "Illegal insn type in multiplier";
  82                 d2 := (others => '0');
  83         end case;
  84
  85         m_out.write_reg_data <= d2;
  86         m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
  87
  88         if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
  89             m_out.valid <= '1';
  90             m_out.write_reg_enable <= '1';
  91
  92             if v.multiply_pipeline(PIPELINE_DEPTH-1).rc = '1' then
  93                 m_out.write_cr_enable <= '1';
  94                 m_out.write_cr_mask <= num_to_fxm(0);
  95                 m_out.write_cr_data <= ppc_cmpi('1', d2, x"0000") & x"0000000";
  96             end if;
  97         end if;
  98
  99         rin <= v;
 100     end process;
 101 end architecture behaviour;