2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
10 PIPELINE_DEPTH : natural := 4
15 m_in : in MultiplyInputType;
16 m_out : out MultiplyOutputType
20 architecture behaviour of multiply is
21 signal m: MultiplyInputType := MultiplyInputInit;
23 type multiply_pipeline_stage is record
25 data : unsigned(127 downto 0);
26 is_32bit : std_ulogic;
29 constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
30 is_32bit => '0', not_res => '0',
31 data => (others => '0'));
33 type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
34 constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
36 type reg_type is record
37 multiply_pipeline : multiply_pipeline_type;
40 signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
42 multiply_0: process(clk)
44 if rising_edge(clk) then
50 multiply_1: process(all)
51 variable v : reg_type;
52 variable d : std_ulogic_vector(127 downto 0);
53 variable d2 : std_ulogic_vector(63 downto 0);
54 variable ov : std_ulogic;
57 v.multiply_pipeline(0).valid := m.valid;
58 v.multiply_pipeline(0).data := (unsigned(m.data1) * unsigned(m.data2)) + unsigned(m.addend);
59 v.multiply_pipeline(0).is_32bit := m.is_32bit;
60 v.multiply_pipeline(0).not_res := m.not_result;
62 loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
63 v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
66 d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
67 if v.multiply_pipeline(PIPELINE_DEPTH-1).not_res = '1' then
72 if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
73 ov := (or d(63 downto 31)) and not (and d(63 downto 31));
75 ov := (or d(127 downto 63)) and not (and d(127 downto 63));
80 m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
84 end architecture behaviour;