multiply_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.glibc_random.all;
   9 use work.ppc_fx_insns.all;
  10
  11 entity multiply_tb is
  12 end multiply_tb;
  13
  14 architecture behave of multiply_tb is
  15     signal clk              : std_ulogic;
  16     constant clk_period     : time := 10 ns;
  17
  18     constant pipeline_depth : integer := 4;
  19
  20     signal m1               : Decode2ToMultiplyType;
  21     signal m2               : MultiplyToWritebackType;
  22 begin
  23     multiply_0: entity work.multiply
  24         generic map (PIPELINE_DEPTH => pipeline_depth)
  25         port map (clk => clk, m_in => m1, m_out => m2);
  26
  27     clk_process: process
  28     begin
  29         clk <= '0';
  30         wait for clk_period/2;
  31         clk <= '1';
  32         wait for clk_period/2;
  33     end process;
  34
  35     stim_process: process
  36         variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
  37         variable si: std_ulogic_vector(15 downto 0);
  38     begin
  39         wait for clk_period;
  40
  41         m1.valid <= '1';
  42         m1.insn_type <= OP_MUL_L64;
  43         m1.write_reg <= "10001";
  44         m1.data1 <= '0' & x"0000000000001000";
  45         m1.data2 <= '0' & x"0000000000001111";
  46         m1.rc <= '0';
  47
  48         wait for clk_period;
  49         assert m2.valid = '0';
  50
  51         m1.valid <= '0';
  52
  53         wait for clk_period;
  54         assert m2.valid = '0';
  55
  56         wait for clk_period;
  57         assert m2.valid = '0';
  58
  59         wait for clk_period;
  60         assert m2.valid = '1';
  61         assert m2.write_reg_enable = '1';
  62         assert m2.write_reg_nr = "10001";
  63         assert m2.write_reg_data = x"0000000001111000";
  64         assert m2.write_cr_enable = '0';
  65
  66         wait for clk_period;
  67         assert m2.valid = '0';
  68
  69         m1.valid <= '1';
  70         m1.rc <= '1';
  71
  72         wait for clk_period;
  73         assert m2.valid = '0';
  74
  75         m1.valid <= '0';
  76
  77         wait for clk_period * (pipeline_depth-1);
  78         assert m2.valid = '1';
  79         assert m2.write_reg_enable = '1';
  80         assert m2.write_reg_nr = "10001";
  81         assert m2.write_reg_data = x"0000000001111000";
  82         assert m2.write_cr_enable = '1';
  83         assert m2.write_cr_data = x"40000000";
  84
  85         -- test mulld
  86         mulld_loop : for i in 0 to 1000 loop
  87             ra := pseudorand(ra'length);
  88             rb := pseudorand(rb'length);
  89
  90             behave_rt := ppc_mulld(ra, rb);
  91
  92             m1.data1 <= '0' & ra;
  93             m1.data2 <= '0' & rb;
  94             m1.valid <= '1';
  95             m1.insn_type <= OP_MUL_L64;
  96
  97             wait for clk_period;
  98
  99             m1.valid <= '0';
 100
 101             wait for clk_period * (pipeline_depth-1);
 102
 103             assert m2.valid = '1';
 104
 105             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 106                 report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 107         end loop;
 108
 109         -- test mulhdu
 110         mulhdu_loop : for i in 0 to 1000 loop
 111             ra := pseudorand(ra'length);
 112             rb := pseudorand(rb'length);
 113
 114             behave_rt := ppc_mulhdu(ra, rb);
 115
 116             m1.data1 <= '0' & ra;
 117             m1.data2 <= '0' & rb;
 118             m1.valid <= '1';
 119             m1.insn_type <= OP_MUL_H64;
 120
 121             wait for clk_period;
 122
 123             m1.valid <= '0';
 124
 125             wait for clk_period * (pipeline_depth-1);
 126
 127             assert m2.valid = '1';
 128
 129             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 130                 report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 131         end loop;
 132
 133         -- test mulhd
 134         mulhd_loop : for i in 0 to 1000 loop
 135             ra := pseudorand(ra'length);
 136             rb := pseudorand(rb'length);
 137
 138             behave_rt := ppc_mulhd(ra, rb);
 139
 140             m1.data1 <= ra(63) & ra;
 141             m1.data2 <= rb(63) & rb;
 142             m1.valid <= '1';
 143             m1.insn_type <= OP_MUL_H64;
 144
 145             wait for clk_period;
 146
 147             m1.valid <= '0';
 148
 149             wait for clk_period * (pipeline_depth-1);
 150
 151             assert m2.valid = '1';
 152
 153             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 154                 report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 155         end loop;
 156
 157         -- test mullw
 158         mullw_loop : for i in 0 to 1000 loop
 159             ra := pseudorand(ra'length);
 160             rb := pseudorand(rb'length);
 161
 162             behave_rt := ppc_mullw(ra, rb);
 163
 164             m1.data1 <= (others => ra(31));
 165             m1.data1(31 downto 0) <= ra(31 downto 0);
 166             m1.data2 <= (others => rb(31));
 167             m1.data2(31 downto 0) <= rb(31 downto 0);
 168             m1.valid <= '1';
 169             m1.insn_type <= OP_MUL_L64;
 170
 171             wait for clk_period;
 172
 173             m1.valid <= '0';
 174
 175             wait for clk_period * (pipeline_depth-1);
 176
 177             assert m2.valid = '1';
 178
 179             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 180                 report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 181         end loop;
 182
 183         -- test mulhw
 184         mulhw_loop : for i in 0 to 1000 loop
 185             ra := pseudorand(ra'length);
 186             rb := pseudorand(rb'length);
 187
 188             behave_rt := ppc_mulhw(ra, rb);
 189
 190             m1.data1 <= (others => ra(31));
 191             m1.data1(31 downto 0) <= ra(31 downto 0);
 192             m1.data2 <= (others => rb(31));
 193             m1.data2(31 downto 0) <= rb(31 downto 0);
 194             m1.valid <= '1';
 195             m1.insn_type <= OP_MUL_H32;
 196
 197             wait for clk_period;
 198
 199             m1.valid <= '0';
 200
 201             wait for clk_period * (pipeline_depth-1);
 202
 203             assert m2.valid = '1';
 204
 205             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 206                 report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 207         end loop;
 208
 209         -- test mulhwu
 210         mulhwu_loop : for i in 0 to 1000 loop
 211             ra := pseudorand(ra'length);
 212             rb := pseudorand(rb'length);
 213
 214             behave_rt := ppc_mulhwu(ra, rb);
 215
 216             m1.data1 <= (others => '0');
 217             m1.data1(31 downto 0) <= ra(31 downto 0);
 218             m1.data2 <= (others => '0');
 219             m1.data2(31 downto 0) <= rb(31 downto 0);
 220             m1.valid <= '1';
 221             m1.insn_type <= OP_MUL_H32;
 222
 223             wait for clk_period;
 224
 225             m1.valid <= '0';
 226
 227             wait for clk_period * (pipeline_depth-1);
 228
 229             assert m2.valid = '1';
 230
 231             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 232                 report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 233         end loop;
 234
 235         -- test mulli
 236         mulli_loop : for i in 0 to 1000 loop
 237             ra := pseudorand(ra'length);
 238             si := pseudorand(si'length);
 239
 240             behave_rt := ppc_mulli(ra, si);
 241
 242             m1.data1 <= ra(63) & ra;
 243             m1.data2 <= (others => si(15));
 244             m1.data2(15 downto 0) <= si;
 245             m1.valid <= '1';
 246             m1.insn_type <= OP_MUL_L64;
 247
 248             wait for clk_period;
 249
 250             m1.valid <= '0';
 251
 252             wait for clk_period * (pipeline_depth-1);
 253
 254             assert m2.valid = '1';
 255
 256             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 257                 report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 258         end loop;
 259
 260         assert false report "end of test" severity failure;
 261         wait;
 262     end process;
 263 end behave;