multiply_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.glibc_random.all;
   9 use work.ppc_fx_insns.all;
  10
  11 entity multiply_tb is
  12 end multiply_tb;
  13
  14 architecture behave of multiply_tb is
  15     signal clk              : std_ulogic;
  16     constant clk_period     : time := 10 ns;
  17
  18     constant pipeline_depth : integer := 4;
  19
  20     signal m1               : Execute1ToMultiplyType;
  21     signal m2               : MultiplyToExecute1Type;
  22 begin
  23     multiply_0: entity work.multiply
  24         generic map (PIPELINE_DEPTH => pipeline_depth)
  25         port map (clk => clk, m_in => m1, m_out => m2);
  26
  27     clk_process: process
  28     begin
  29         clk <= '0';
  30         wait for clk_period/2;
  31         clk <= '1';
  32         wait for clk_period/2;
  33     end process;
  34
  35     stim_process: process
  36         variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
  37         variable si: std_ulogic_vector(15 downto 0);
  38     begin
  39         wait for clk_period;
  40
  41         m1.valid <= '1';
  42         m1.insn_type <= OP_MUL_L64;
  43         m1.data1 <= '0' & x"0000000000001000";
  44         m1.data2 <= '0' & x"0000000000001111";
  45
  46         wait for clk_period;
  47         assert m2.valid = '0';
  48
  49         m1.valid <= '0';
  50
  51         wait for clk_period;
  52         assert m2.valid = '0';
  53
  54         wait for clk_period;
  55         assert m2.valid = '0';
  56
  57         wait for clk_period;
  58         assert m2.valid = '1';
  59         assert m2.write_reg_data = x"0000000001111000";
  60
  61         wait for clk_period;
  62         assert m2.valid = '0';
  63
  64         m1.valid <= '1';
  65
  66         wait for clk_period;
  67         assert m2.valid = '0';
  68
  69         m1.valid <= '0';
  70
  71         wait for clk_period * (pipeline_depth-1);
  72         assert m2.valid = '1';
  73         assert m2.write_reg_data = x"0000000001111000";
  74
  75         -- test mulld
  76         mulld_loop : for i in 0 to 1000 loop
  77             ra := pseudorand(ra'length);
  78             rb := pseudorand(rb'length);
  79
  80             behave_rt := ppc_mulld(ra, rb);
  81
  82             m1.data1 <= '0' & ra;
  83             m1.data2 <= '0' & rb;
  84             m1.valid <= '1';
  85             m1.insn_type <= OP_MUL_L64;
  86
  87             wait for clk_period;
  88
  89             m1.valid <= '0';
  90
  91             wait for clk_period * (pipeline_depth-1);
  92
  93             assert m2.valid = '1';
  94
  95             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
  96                 report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
  97         end loop;
  98
  99         -- test mulhdu
 100         mulhdu_loop : for i in 0 to 1000 loop
 101             ra := pseudorand(ra'length);
 102             rb := pseudorand(rb'length);
 103
 104             behave_rt := ppc_mulhdu(ra, rb);
 105
 106             m1.data1 <= '0' & ra;
 107             m1.data2 <= '0' & rb;
 108             m1.valid <= '1';
 109             m1.insn_type <= OP_MUL_H64;
 110
 111             wait for clk_period;
 112
 113             m1.valid <= '0';
 114
 115             wait for clk_period * (pipeline_depth-1);
 116
 117             assert m2.valid = '1';
 118
 119             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 120                 report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 121         end loop;
 122
 123         -- test mulhd
 124         mulhd_loop : for i in 0 to 1000 loop
 125             ra := pseudorand(ra'length);
 126             rb := pseudorand(rb'length);
 127
 128             behave_rt := ppc_mulhd(ra, rb);
 129
 130             m1.data1 <= ra(63) & ra;
 131             m1.data2 <= rb(63) & rb;
 132             m1.valid <= '1';
 133             m1.insn_type <= OP_MUL_H64;
 134
 135             wait for clk_period;
 136
 137             m1.valid <= '0';
 138
 139             wait for clk_period * (pipeline_depth-1);
 140
 141             assert m2.valid = '1';
 142
 143             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 144                 report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 145         end loop;
 146
 147         -- test mullw
 148         mullw_loop : for i in 0 to 1000 loop
 149             ra := pseudorand(ra'length);
 150             rb := pseudorand(rb'length);
 151
 152             behave_rt := ppc_mullw(ra, rb);
 153
 154             m1.data1 <= (others => ra(31));
 155             m1.data1(31 downto 0) <= ra(31 downto 0);
 156             m1.data2 <= (others => rb(31));
 157             m1.data2(31 downto 0) <= rb(31 downto 0);
 158             m1.valid <= '1';
 159             m1.insn_type <= OP_MUL_L64;
 160
 161             wait for clk_period;
 162
 163             m1.valid <= '0';
 164
 165             wait for clk_period * (pipeline_depth-1);
 166
 167             assert m2.valid = '1';
 168
 169             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 170                 report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 171         end loop;
 172
 173         -- test mulhw
 174         mulhw_loop : for i in 0 to 1000 loop
 175             ra := pseudorand(ra'length);
 176             rb := pseudorand(rb'length);
 177
 178             behave_rt := ppc_mulhw(ra, rb);
 179
 180             m1.data1 <= (others => ra(31));
 181             m1.data1(31 downto 0) <= ra(31 downto 0);
 182             m1.data2 <= (others => rb(31));
 183             m1.data2(31 downto 0) <= rb(31 downto 0);
 184             m1.valid <= '1';
 185             m1.insn_type <= OP_MUL_H32;
 186
 187             wait for clk_period;
 188
 189             m1.valid <= '0';
 190
 191             wait for clk_period * (pipeline_depth-1);
 192
 193             assert m2.valid = '1';
 194
 195             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 196                 report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 197         end loop;
 198
 199         -- test mulhwu
 200         mulhwu_loop : for i in 0 to 1000 loop
 201             ra := pseudorand(ra'length);
 202             rb := pseudorand(rb'length);
 203
 204             behave_rt := ppc_mulhwu(ra, rb);
 205
 206             m1.data1 <= (others => '0');
 207             m1.data1(31 downto 0) <= ra(31 downto 0);
 208             m1.data2 <= (others => '0');
 209             m1.data2(31 downto 0) <= rb(31 downto 0);
 210             m1.valid <= '1';
 211             m1.insn_type <= OP_MUL_H32;
 212
 213             wait for clk_period;
 214
 215             m1.valid <= '0';
 216
 217             wait for clk_period * (pipeline_depth-1);
 218
 219             assert m2.valid = '1';
 220
 221             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 222                 report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 223         end loop;
 224
 225         -- test mulli
 226         mulli_loop : for i in 0 to 1000 loop
 227             ra := pseudorand(ra'length);
 228             si := pseudorand(si'length);
 229
 230             behave_rt := ppc_mulli(ra, si);
 231
 232             m1.data1 <= ra(63) & ra;
 233             m1.data2 <= (others => si(15));
 234             m1.data2(15 downto 0) <= si;
 235             m1.valid <= '1';
 236             m1.insn_type <= OP_MUL_L64;
 237
 238             wait for clk_period;
 239
 240             m1.valid <= '0';
 241
 242             wait for clk_period * (pipeline_depth-1);
 243
 244             assert m2.valid = '1';
 245
 246             assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
 247                 report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
 248         end loop;
 249
 250         std.env.finish;
 251         wait;
 252     end process;
 253 end behave;