nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 *
   8
   9 # questions 05 oct 2022
  10
  11 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  12 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  13
  14 **
  15     Again there should be a breakdown of the main tasks, and the associated effort.
  16     And a clarification what rates you used.
  17     (I'm assuming these are the same, but I've learned not to assume...)
  18 **
  19
  20 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  21
  22 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  23 group backed by Intel!)
  24
  25 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  26 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  27   of FP Rounding Modes and Power ISA Flags
  28 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
  29 * 3-4 months: Addition of the IEEE754 FPU to the Core
  30 * 3-4 months: Addition of other ALUs and pipelines
  31 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  32   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
  33 * 3-4 months: Running under Verilator and on FPGAs (big ones)
  34 * 4-5 months: Continued documentation, attendance of Conferences online
  35 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
  36 * 2-3 months plus hosting costs: Establishment and management of CI
  37 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
  38
  39 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
  40 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
  41 tasks removing, to fit. we cannot risk committing to tasks at too low a
  42 rate to be able to attract interest and committment.
  43
  44 Again however I do not have a problem with reducing the scope of this one
  45 to only EUR 50,000 to cover some of the less ambitious tasks, with the
  46 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
  47 priority then a second Grant following up to continue.
  48
  49 **
  50     What would be the concrete (high level) outcome of that project -
  51     where would the grant get us? Would there be a new test chip made
  52     during the lifespan of the project?
  53 **
  54
  55 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
  56 based Routing completed in order to tackle lower geometries (even 90nm),
  57 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
  58 sky130
  59 is far too small an allocation (12 mm^2 when we need around 100), we
  60 really need sky90 which as i understand is still being negotiated and set up.
  61
  62 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
  63 as a "learning exercise" the 2019-10-029 project was perfect.
  64 However as far as "value for money" is concerned, a repeat is honestly
  65 less valuable.  That said: when it is ready, RED Semiconductor
  66 *will* be picking up the Libre-SOC core and taking it to Silicon
  67 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
  68 get us a long way.
  69
  70 The concrete outcomes:
  71
  72 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
  73   Abstraction of its core Language Features.  Opportunities then open up
  74   to perform strict type checking, length checking, other types of Arithmetic
  75   (Complex numbers, Galois Field) and other "filters" as
  76   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
  77   2019-02-012 would be the first big showcase.
  78 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
  79   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
  80   and something worth aiming for.
  81   The only
  82   other Libre Formal Proof is Academically developed
  83   for an older version of IEEE754: we will
  84   target 2008 and 2019 semantics.
  85 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
  86   present it is Simulations only and the cavatools Cycle-accurate Simulator
  87   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
  88   no Virtual Memory, for a start).  SMP Support in particular would be strategically
  89   very valuable to have, it greatly expands the commercial viability.
  90 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
  91   an IBM POWER9 Server which lends us credibility but it needs to be put to
  92   good use!
  93
  94 In other words, mostly "low-level strategic outcomes" on the way to success :)