nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 ### Bug #1003
   8
   9 * There is no overlap, as #976 tackled a different issue (and was already complete
  10 before #1003).
  11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  12 * Bug #1003 does however build on the work from #972.
  13 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  14
  15 **TODO: just put clear message describing task.  No "Edit: this etc etc"**
  16
  17 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  18
  19 ### Bug #999
  20
  21 * Build means that Sadoon provides documentation for setting up a SFFS port
  22 of Gentoo and Debian.
  23 * Stage 3 tar archive file for Gentoo is now available,
  24 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  25 * Debian scripts are still being worked on as of 23rd Aug.
  26 * All files required are hosted either on Libre-SOC's ftp or git.
  27 * Patching qemu has been discovered to be out-of-scope for this task
  28 (far too much work). Sadoon will be creating (or adding sesction to
  29 Gentoo/Debian pages) a wiki page describing the
  30 work he went through with qemu.
  31
  32 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
  33
  34 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
  35
  36 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
  37
  38 ### Bugs 1025/1026
  39
  40 * Jacob is still working on figuring out the subtasks which should be focused
  41 on for the scope of the On-Going grant.
  42
  43 **NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**
  44
  45 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
  46 the MoU. See
  47 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
  48
  49 ### Bug 1032
  50
  51 * Jacob mentioned there are two major parts
  52
  53 1. Decoder/fetch pipeline
  54 2. Execution unit
  55
  56 Cesar likely do the former, Jacob could do the latter.
  57
  58 **CORRECTION: JACOB to do both.**
  59
  60 ### Bug 1033
  61
  62 * Create the framework for testing (or choose existing)
  63   (jacob: important clarification -- afaict this task is adding new `StateRunner`
  64   and `State` subclasses for FPGA/verilator/etc.
  65   This task is *not* for creating a new framework or choosing an existing framework,
  66   we already have one with implementations for pypowersim, nmigen simulation of the
  67   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
  68 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
  69 * Cavatools out of scope.
  70 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
  71 * Initially pypowersim tested against qemu, then FPGA.
  72 * For Simple-V/SVP64 only pypowersim implementation right now.
  73 SoC HDL has small subset of SVP64.
  74
  75
  76 ### Automated method for removing non-MOU things
  77
  78 * Jacob added a feature to automatically remove non-MOU strings.
  79
  80
  81 # questions 05 oct 2022
  82
  83 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  84 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  85
  86 **
  87     Again there should be a breakdown of the main tasks, and the associated effort.
  88     And a clarification what rates you used.
  89     (I'm assuming these are the same, but I've learned not to assume...)
  90 **
  91
  92 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  93
  94 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  95 group backed by Intel!)
  96
  97 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  98 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  99   of FP Rounding Modes and Power ISA Flags
 100 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 101 * 3-4 months: Addition of the IEEE754 FPU to the Core
 102 * 3-4 months: Addition of other ALUs and pipelines
 103 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
 104   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 105 * 3-4 months: Running under Verilator and on FPGAs (big ones)
 106 * 4-5 months: Continued documentation, attendance of Conferences online
 107 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
 108 * 2-3 months plus hosting costs: Establishment and management of CI
 109 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
 110
 111 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
 112 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 113 tasks removing, to fit. we cannot risk committing to tasks at too low a
 114 rate to be able to attract interest and committment.
 115
 116 Again however I do not have a problem with reducing the scope of this one
 117 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 118 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 119 priority then a second Grant following up to continue.
 120
 121 **
 122     What would be the concrete (high level) outcome of that project -
 123     where would the grant get us? Would there be a new test chip made
 124     during the lifespan of the project?
 125 **
 126
 127 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 128 based Routing completed in order to tackle lower geometries (even 90nm),
 129 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 130 sky130
 131 is far too small an allocation (12 mm^2 when we need around 100), we
 132 really need sky90 which as i understand is still being negotiated and set up.
 133
 134 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 135 as a "learning exercise" the 2019-10-029 project was perfect.
 136 However as far as "value for money" is concerned, a repeat is honestly
 137 less valuable.  That said: when it is ready, RED Semiconductor
 138 *will* be picking up the Libre-SOC core and taking it to Silicon
 139 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 140 get us a long way.
 141
 142 The concrete outcomes:
 143
 144 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 145   Abstraction of its core Language Features.  Opportunities then open up
 146   to perform strict type checking, length checking, other types of Arithmetic
 147   (Complex numbers, Galois Field) and other "filters" as
 148   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 149   2019-02-012 would be the first big showcase.
 150 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 151   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 152   and something worth aiming for.
 153   The only
 154   other Libre Formal Proof is Academically developed
 155   for an older version of IEEE754: we will
 156   target 2008 and 2019 semantics.
 157 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 158   present it is Simulations only and the cavatools Cycle-accurate Simulator
 159   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 160   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 161   very valuable to have, it greatly expands the commercial viability.
 162 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 163   an IBM POWER9 Server which lends us credibility but it needs to be put to
 164   good use!
 165
 166 In other words, mostly "low-level strategic outcomes" on the way to success :)