[libreriscv.git] / nlnet_2022_ongoing / discussion.mdwn

# Meeting 30th aug 2023 08:45 UTC

* Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132

* If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
see any problems).

* Jacob please update the json file.

* Luke (once checked with Dmitry and Jacob) please do a final check and submit.

**TODO**: Dmitry would like to make budget adjustments to
[bug #1068](https://bugs.libre-soc.org/show_bug.cgi?id=1068),
a subtask of [bug #1003](https://bugs.libre-soc.org/show_bug.cgi?id=1003).
See the
[IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-30.log.html#t2023-08-30T11:18:53)

* A meeting later today will be arranged to make adjustments to the budget.

# questions 17 aug 2023

* <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>

## Discussion from meeting on the 23rd August 2023 21:00 UTC+1

### Bug #1003

* There is no overlap, as #976 tackled a different issue (and was already complete
before #1003).
* "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
* Bug #1003 does however build on the work from #972.
* Added to comment 0 of bug #1003 to clarify that it builds on top of #972.

**TODO: just put clear message describing task.  No "Edit: this etc etc"**

* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).

**TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
 3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary.  we already know it's an umbrella task, as it has child
subtasks.  5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**

* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).

### Bug #999

* Build means that Sadoon provides documentation for setting up a SFFS port
of Gentoo and Debian.
* Stage 3 tar archive file for Gentoo is now available, 
see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
* Debian scripts are still being worked on as of 23rd Aug.
* All files required are hosted either on Libre-SOC's ftp or git.
* Patching qemu has been discovered to be out-of-scope for this task
(far too much work). Sadoon will be creating (or adding sesction to
Gentoo/Debian pages) a wiki page describing the
work he went through with qemu.

**TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**

**TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**

* Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.

### Bugs 1025/1026

* Jacob is still working on figuring out the subtasks which should be focused
on for the scope of the On-Going grant.

**NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**

Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
the MoU. See
[IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)

**please REMOVE that.  it is NOT necessary to make such a statement.
it is already known**

### Bug 1032

* Jacob mentioned there are two major parts

1. Decoder/fetch pipeline
2. Execution unit

Cesar likely do the former, Jacob could do the latter.

**CORRECTION: JACOB to do both.**

* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).

### Bug 1033

* Create the framework for testing (or choose existing)
  (jacob: important clarification -- afaict this task is adding new `StateRunner`
  and `State` subclasses for FPGA/verilator/etc.
  This task is *not* for creating a new framework or choosing an existing framework,
  we already have one with implementations for pypowersim, nmigen simulation of the
  libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
* Add specialisation for pypowersim, microwatt (verilator), FPGA.
* Cavatools out of scope.
* Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
* Initially pypowersim tested against qemu, then FPGA.
* For Simple-V/SVP64 only pypowersim implementation right now.
SoC HDL has small subset of SVP64.


### Automated method for removing non-MOU things

* Jacob added a feature to automatically remove non-MOU strings.

**(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**

# questions 05 oct 2022

context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>

**
    Again there should be a breakdown of the main tasks, and the associated effort.
    And a clarification what rates you used.
    (I'm assuming these are the same, but I've learned not to assume...)
**

yes EUR 3,000 / mo as a yardstick works out ok in practice.

tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
group backed by Intel!)

* 2-3 months: Dynamic Partitioned SIMD for nmigen 
* 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  of FP Rounding Modes and Power ISA Flags
* 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
* 3-4 months: Addition of the IEEE754 FPU to the Core
* 3-4 months: Addition of other ALUs and pipelines
* 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
* 3-4 months: Running under Verilator and on FPGAs (big ones) 
* 4-5 months: Continued documentation, attendance of Conferences online
* 4-5 months: Begin investigating Multi-Issue Out-of-Order
* 2-3 months plus hosting costs: Establishment and management of CI
* 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)

lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
budget @ EUR 3,000/mo is within target (just). may need adjusting or some
tasks removing, to fit. we cannot risk committing to tasks at too low a
rate to be able to attract interest and committment.

Again however I do not have a problem with reducing the scope of this one
to only EUR 50,000 to cover some of the less ambitious tasks, with the
necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
priority then a second Grant following up to continue.

**
    What would be the concrete (high level) outcome of that project -
    where would the grant get us? Would there be a new test chip made
    during the lifespan of the project?
**

Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
based Routing completed in order to tackle lower geometries (even 90nm),
https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
sky130
is far too small an allocation (12 mm^2 when we need around 100), we
really need sky90 which as i understand is still being negotiated and set up.

Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
as a "learning exercise" the 2019-10-029 project was perfect.
However as far as "value for money" is concerned, a repeat is honestly
less valuable.  That said: when it is ready, RED Semiconductor
*will* be picking up the Libre-SOC core and taking it to Silicon
(28 nm or below).  For this Grant Proposal, powerful FPGAs will
get us a long way.

The concrete outcomes:

* A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
  Abstraction of its core Language Features.  Opportunities then open up
  to perform strict type checking, length checking, other types of Arithmetic
  (Complex numbers, Galois Field) and other "filters" as
  3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
  2019-02-012 would be the first big showcase.
* A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
  Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
  and something worth aiming for.
  The only
  other Libre Formal Proof is Academically developed 
  for an older version of IEEE754: we will
  target 2008 and 2019 semantics.
* An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
  present it is Simulations only and the cavatools Cycle-accurate Simulator
  (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
  no Virtual Memory, for a start).  SMP Support in particular would be strategically
  very valuable to have, it greatly expands the commercial viability.
* A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
  an IBM POWER9 Server which lends us credibility but it needs to be put to
  good use!

In other words, mostly "low-level strategic outcomes" on the way to success :)