nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 ### Bug #1003
   8
   9 * There is no overlap, as #976 tackled a different issue (and was already complete
  10 before #1003).
  11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  12 * Bug #1003 does however build on the work from #972.
  13 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  14
  15 ### Bug #999
  16
  17 * Build means that Sadoon provides documentation for setting up a SFFS port
  18 of Gentoo and Debian.
  19 * Stage 3 tar archive file for Gentoo is now available,
  20 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  21 * Debian scripts are still being worked on as of 23rd Aug.
  22 * All files required are hosted either on Libre-SOC's ftp or git.
  23 * Patching qemu has been discovered to be out-of-scope for this task
  24 (far too much work). Sadoon will be creating (or adding sesction to
  25 Gentoo/Debian pages) a wiki page describing the
  26 work he went through with qemu.
  27
  28 ### Bugs 1025/1026
  29
  30 * Jacob is still working on figuring out the subtasks which should be focused
  31 on for the scope of the On-Going grant.
  32
  33 ### Bug 1032
  34
  35 * Jacob mentioned there are two major parts
  36
  37 1. Decoder/fetch pipeline
  38 2. Execution unit
  39
  40 Cesar likely do the former, Jacob could do the latter.
  41
  42 ### Bug 1033
  43
  44 * Create the framework for testing (or choose existing)
  45   (jacob: important clarification -- afaict this task is adding new `StateRunner`
  46   and `State` subclasses for FPGA/verilator/etc.
  47   This task is *not* for creating a new framework or choosing an existing framework,
  48   we already have one with implementations for pypowersim, nmigen simulation of the
  49   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
  50 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
  51 * Cavatools out of scope.
  52 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
  53 * Initially pypowersim tested against qemu, then FPGA.
  54 * For Simple-V/SVP64 only pypowersim implementation right now.
  55 SoC HDL has small subset of SVP64.
  56
  57
  58 ### Automated method for removing non-MOU things
  59
  60 * Jacob added a feature to automatically remove non-MOU strings.
  61
  62
  63 # questions 05 oct 2022
  64
  65 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  66 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  67
  68 **
  69     Again there should be a breakdown of the main tasks, and the associated effort.
  70     And a clarification what rates you used.
  71     (I'm assuming these are the same, but I've learned not to assume...)
  72 **
  73
  74 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  75
  76 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  77 group backed by Intel!)
  78
  79 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  80 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  81   of FP Rounding Modes and Power ISA Flags
  82 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
  83 * 3-4 months: Addition of the IEEE754 FPU to the Core
  84 * 3-4 months: Addition of other ALUs and pipelines
  85 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  86   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
  87 * 3-4 months: Running under Verilator and on FPGAs (big ones)
  88 * 4-5 months: Continued documentation, attendance of Conferences online
  89 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
  90 * 2-3 months plus hosting costs: Establishment and management of CI
  91 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
  92
  93 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
  94 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
  95 tasks removing, to fit. we cannot risk committing to tasks at too low a
  96 rate to be able to attract interest and committment.
  97
  98 Again however I do not have a problem with reducing the scope of this one
  99 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 100 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 101 priority then a second Grant following up to continue.
 102
 103 **
 104     What would be the concrete (high level) outcome of that project -
 105     where would the grant get us? Would there be a new test chip made
 106     during the lifespan of the project?
 107 **
 108
 109 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 110 based Routing completed in order to tackle lower geometries (even 90nm),
 111 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 112 sky130
 113 is far too small an allocation (12 mm^2 when we need around 100), we
 114 really need sky90 which as i understand is still being negotiated and set up.
 115
 116 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 117 as a "learning exercise" the 2019-10-029 project was perfect.
 118 However as far as "value for money" is concerned, a repeat is honestly
 119 less valuable.  That said: when it is ready, RED Semiconductor
 120 *will* be picking up the Libre-SOC core and taking it to Silicon
 121 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 122 get us a long way.
 123
 124 The concrete outcomes:
 125
 126 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 127   Abstraction of its core Language Features.  Opportunities then open up
 128   to perform strict type checking, length checking, other types of Arithmetic
 129   (Complex numbers, Galois Field) and other "filters" as
 130   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 131   2019-02-012 would be the first big showcase.
 132 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 133   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 134   and something worth aiming for.
 135   The only
 136   other Libre Formal Proof is Academically developed
 137   for an older version of IEEE754: we will
 138   target 2008 and 2019 semantics.
 139 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 140   present it is Simulations only and the cavatools Cycle-accurate Simulator
 141   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 142   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 143   very valuable to have, it greatly expands the commercial viability.
 144 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 145   an IBM POWER9 Server which lends us credibility but it needs to be put to
 146   good use!
 147
 148 In other words, mostly "low-level strategic outcomes" on the way to success :)