nlnet_2022_ongoing/discussion.mdwn

   1 # Meeting 30th aug 2023 08:45 UTC
   2
   3 * Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
   4 1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132
   5
   6 * If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
   7 see any problems).
   8
   9 * Jacob please update the json file.
  10
  11 * Luke (once checked with Dmitry and Jacob) please do a final check and submit.
  12
  13 # questions 17 aug 2023
  14
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
  16
  17 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
  18
  19 ### Bug #1003
  20
  21 * There is no overlap, as #976 tackled a different issue (and was already complete
  22 before #1003).
  23 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  24 * Bug #1003 does however build on the work from #972.
  25 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  26
  27 **TODO: just put clear message describing task.  No "Edit: this etc etc"**
  28
  29 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  30
  31 **TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
  32  3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary.  we already know it's an umbrella task, as it has child
  33 subtasks.  5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
  34
  35 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  36
  37 ### Bug #999
  38
  39 * Build means that Sadoon provides documentation for setting up a SFFS port
  40 of Gentoo and Debian.
  41 * Stage 3 tar archive file for Gentoo is now available,
  42 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  43 * Debian scripts are still being worked on as of 23rd Aug.
  44 * All files required are hosted either on Libre-SOC's ftp or git.
  45 * Patching qemu has been discovered to be out-of-scope for this task
  46 (far too much work). Sadoon will be creating (or adding sesction to
  47 Gentoo/Debian pages) a wiki page describing the
  48 work he went through with qemu.
  49
  50 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
  51
  52 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
  53
  54 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
  55
  56 ### Bugs 1025/1026
  57
  58 * Jacob is still working on figuring out the subtasks which should be focused
  59 on for the scope of the On-Going grant.
  60
  61 **NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**
  62
  63 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
  64 the MoU. See
  65 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
  66
  67 **please REMOVE that.  it is NOT necessary to make such a statement.
  68 it is already known**
  69
  70 ### Bug 1032
  71
  72 * Jacob mentioned there are two major parts
  73
  74 1. Decoder/fetch pipeline
  75 2. Execution unit
  76
  77 Cesar likely do the former, Jacob could do the latter.
  78
  79 **CORRECTION: JACOB to do both.**
  80
  81 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).
  82
  83 ### Bug 1033
  84
  85 * Create the framework for testing (or choose existing)
  86   (jacob: important clarification -- afaict this task is adding new `StateRunner`
  87   and `State` subclasses for FPGA/verilator/etc.
  88   This task is *not* for creating a new framework or choosing an existing framework,
  89   we already have one with implementations for pypowersim, nmigen simulation of the
  90   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
  91 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
  92 * Cavatools out of scope.
  93 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
  94 * Initially pypowersim tested against qemu, then FPGA.
  95 * For Simple-V/SVP64 only pypowersim implementation right now.
  96 SoC HDL has small subset of SVP64.
  97
  98
  99 ### Automated method for removing non-MOU things
 100
 101 * Jacob added a feature to automatically remove non-MOU strings.
 102
 103 **(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
 104
 105 # questions 05 oct 2022
 106
 107 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
 108 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
 109
 110 **
 111     Again there should be a breakdown of the main tasks, and the associated effort.
 112     And a clarification what rates you used.
 113     (I'm assuming these are the same, but I've learned not to assume...)
 114 **
 115
 116 yes EUR 3,000 / mo as a yardstick works out ok in practice.
 117
 118 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
 119 group backed by Intel!)
 120
 121 * 2-3 months: Dynamic Partitioned SIMD for nmigen
 122 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
 123   of FP Rounding Modes and Power ISA Flags
 124 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 125 * 3-4 months: Addition of the IEEE754 FPU to the Core
 126 * 3-4 months: Addition of other ALUs and pipelines
 127 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
 128   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 129 * 3-4 months: Running under Verilator and on FPGAs (big ones)
 130 * 4-5 months: Continued documentation, attendance of Conferences online
 131 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
 132 * 2-3 months plus hosting costs: Establishment and management of CI
 133 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
 134
 135 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
 136 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 137 tasks removing, to fit. we cannot risk committing to tasks at too low a
 138 rate to be able to attract interest and committment.
 139
 140 Again however I do not have a problem with reducing the scope of this one
 141 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 142 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 143 priority then a second Grant following up to continue.
 144
 145 **
 146     What would be the concrete (high level) outcome of that project -
 147     where would the grant get us? Would there be a new test chip made
 148     during the lifespan of the project?
 149 **
 150
 151 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 152 based Routing completed in order to tackle lower geometries (even 90nm),
 153 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 154 sky130
 155 is far too small an allocation (12 mm^2 when we need around 100), we
 156 really need sky90 which as i understand is still being negotiated and set up.
 157
 158 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 159 as a "learning exercise" the 2019-10-029 project was perfect.
 160 However as far as "value for money" is concerned, a repeat is honestly
 161 less valuable.  That said: when it is ready, RED Semiconductor
 162 *will* be picking up the Libre-SOC core and taking it to Silicon
 163 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 164 get us a long way.
 165
 166 The concrete outcomes:
 167
 168 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 169   Abstraction of its core Language Features.  Opportunities then open up
 170   to perform strict type checking, length checking, other types of Arithmetic
 171   (Complex numbers, Galois Field) and other "filters" as
 172   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 173   2019-02-012 would be the first big showcase.
 174 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 175   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 176   and something worth aiming for.
 177   The only
 178   other Libre Formal Proof is Academically developed
 179   for an older version of IEEE754: we will
 180   target 2008 and 2019 semantics.
 181 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 182   present it is Simulations only and the cavatools Cycle-accurate Simulator
 183   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 184   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 185   very valuable to have, it greatly expands the commercial viability.
 186 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 187   an IBM POWER9 Server which lends us credibility but it needs to be put to
 188   good use!
 189
 190 In other words, mostly "low-level strategic outcomes" on the way to success :)