nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 ### Bug #1003
   8
   9 * There is no overlap, as #976 tackled a different issue (and was already complete
  10 before #1003).
  11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  12 * Bug #1003 does however build on the work from #972.
  13 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  14
  15 **TODO: just put clear message describing task.  No "Edit: this etc etc"**
  16
  17 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  18
  19 **TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
  20  3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary.  we already know it's an umbrella task, as it has child
  21 subtasks.  5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
  22
  23 ### Bug #999
  24
  25 * Build means that Sadoon provides documentation for setting up a SFFS port
  26 of Gentoo and Debian.
  27 * Stage 3 tar archive file for Gentoo is now available,
  28 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  29 * Debian scripts are still being worked on as of 23rd Aug.
  30 * All files required are hosted either on Libre-SOC's ftp or git.
  31 * Patching qemu has been discovered to be out-of-scope for this task
  32 (far too much work). Sadoon will be creating (or adding sesction to
  33 Gentoo/Debian pages) a wiki page describing the
  34 work he went through with qemu.
  35
  36 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
  37
  38 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
  39
  40 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
  41
  42 ### Bugs 1025/1026
  43
  44 * Jacob is still working on figuring out the subtasks which should be focused
  45 on for the scope of the On-Going grant.
  46
  47 **NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**
  48
  49 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
  50 the MoU. See
  51 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
  52
  53 **please REMOVE that.  it is NOT necessary to make such a statement.
  54 it is already known**
  55
  56 ### Bug 1032
  57
  58 * Jacob mentioned there are two major parts
  59
  60 1. Decoder/fetch pipeline
  61 2. Execution unit
  62
  63 Cesar likely do the former, Jacob could do the latter.
  64
  65 **CORRECTION: JACOB to do both.**
  66
  67 ### Bug 1033
  68
  69 * Create the framework for testing (or choose existing)
  70   (jacob: important clarification -- afaict this task is adding new `StateRunner`
  71   and `State` subclasses for FPGA/verilator/etc.
  72   This task is *not* for creating a new framework or choosing an existing framework,
  73   we already have one with implementations for pypowersim, nmigen simulation of the
  74   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
  75 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
  76 * Cavatools out of scope.
  77 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
  78 * Initially pypowersim tested against qemu, then FPGA.
  79 * For Simple-V/SVP64 only pypowersim implementation right now.
  80 SoC HDL has small subset of SVP64.
  81
  82
  83 ### Automated method for removing non-MOU things
  84
  85 * Jacob added a feature to automatically remove non-MOU strings.
  86
  87 **(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
  88
  89 # questions 05 oct 2022
  90
  91 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  92 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  93
  94 **
  95     Again there should be a breakdown of the main tasks, and the associated effort.
  96     And a clarification what rates you used.
  97     (I'm assuming these are the same, but I've learned not to assume...)
  98 **
  99
 100 yes EUR 3,000 / mo as a yardstick works out ok in practice.
 101
 102 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
 103 group backed by Intel!)
 104
 105 * 2-3 months: Dynamic Partitioned SIMD for nmigen
 106 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
 107   of FP Rounding Modes and Power ISA Flags
 108 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 109 * 3-4 months: Addition of the IEEE754 FPU to the Core
 110 * 3-4 months: Addition of other ALUs and pipelines
 111 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
 112   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 113 * 3-4 months: Running under Verilator and on FPGAs (big ones)
 114 * 4-5 months: Continued documentation, attendance of Conferences online
 115 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
 116 * 2-3 months plus hosting costs: Establishment and management of CI
 117 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
 118
 119 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
 120 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 121 tasks removing, to fit. we cannot risk committing to tasks at too low a
 122 rate to be able to attract interest and committment.
 123
 124 Again however I do not have a problem with reducing the scope of this one
 125 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 126 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 127 priority then a second Grant following up to continue.
 128
 129 **
 130     What would be the concrete (high level) outcome of that project -
 131     where would the grant get us? Would there be a new test chip made
 132     during the lifespan of the project?
 133 **
 134
 135 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 136 based Routing completed in order to tackle lower geometries (even 90nm),
 137 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 138 sky130
 139 is far too small an allocation (12 mm^2 when we need around 100), we
 140 really need sky90 which as i understand is still being negotiated and set up.
 141
 142 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 143 as a "learning exercise" the 2019-10-029 project was perfect.
 144 However as far as "value for money" is concerned, a repeat is honestly
 145 less valuable.  That said: when it is ready, RED Semiconductor
 146 *will* be picking up the Libre-SOC core and taking it to Silicon
 147 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 148 get us a long way.
 149
 150 The concrete outcomes:
 151
 152 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 153   Abstraction of its core Language Features.  Opportunities then open up
 154   to perform strict type checking, length checking, other types of Arithmetic
 155   (Complex numbers, Galois Field) and other "filters" as
 156   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 157   2019-02-012 would be the first big showcase.
 158 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 159   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 160   and something worth aiming for.
 161   The only
 162   other Libre Formal Proof is Academically developed
 163   for an older version of IEEE754: we will
 164   target 2008 and 2019 semantics.
 165 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 166   present it is Simulations only and the cavatools Cycle-accurate Simulator
 167   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 168   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 169   very valuable to have, it greatly expands the commercial viability.
 170 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 171   an IBM POWER9 Server which lends us credibility but it needs to be put to
 172   good use!
 173
 174 In other words, mostly "low-level strategic outcomes" on the way to success :)