nmigen/back/verilog.py

   1 from .._toolchain.yosys import *
   2 from . import rtlil
   3
   4
   5 __all__ = ["YosysError", "convert", "convert_fragment"]
   6
   7
   8 def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
   9     # this version requirement needs to be synchronized with the one in setup.py!
  10     yosys = find_yosys(lambda ver: ver >= (0, 9))
  11     yosys_version = yosys.version()
  12
  13     script = []
  14     script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
  15
  16     if yosys_version >= (0, 9, 3527):
  17         # Yosys >=0.9+3527 (since commit 656ee70f) supports the `-nomux` option for the `proc`
  18         # script pass. Because the individual `proc_*` passes are not a stable interface,
  19         # `proc -nomux` is used instead, if available.
  20         script.append("delete w:$verilog_initial_trigger")
  21         script.append("proc -nomux")
  22     else:
  23         # On earlier versions, use individual `proc_*` passes; this is a known range of Yosys
  24         # versions and we know it's compatible with what nMigen does.
  25         script.append("proc_init")
  26         script.append("proc_arst")
  27         script.append("proc_dff")
  28         script.append("proc_clean")
  29     script.append("memory_collect")
  30
  31     if strip_internal_attrs:
  32         attr_map = []
  33         attr_map.append("-remove generator")
  34         attr_map.append("-remove top")
  35         attr_map.append("-remove src")
  36         attr_map.append("-remove nmigen.hierarchy")
  37         attr_map.append("-remove nmigen.decoding")
  38         script.append("attrmap {}".format(" ".join(attr_map)))
  39         script.append("attrmap -modattr {}".format(" ".join(attr_map)))
  40
  41     script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
  42
  43     return yosys.run(["-q", "-"], "\n".join(script),
  44         # At the moment, Yosys always shows a warning indicating that not all processes can be
  45         # translated to Verilog. We carefully emit only the processes that *can* be translated, and
  46         # squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
  47         ignore_warnings=True)
  48
  49
  50 def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
  51     rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
  52     return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
  53
  54
  55 def convert(*args, strip_internal_attrs=False, **kwargs):
  56     rtlil_text = rtlil.convert(*args, **kwargs)
  57     return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)