nmigen/test/compat/test_fifo.py

   1 import unittest
   2 from itertools import count
   3
   4 from ...compat import *
   5 from ...compat.genlib.fifo import SyncFIFO
   6
   7 from .support import SimCase
   8
   9
  10 class SyncFIFOCase(SimCase, unittest.TestCase):
  11     class TestBench(Module):
  12         def __init__(self):
  13             self.submodules.dut = SyncFIFO(64, 2)
  14
  15             self.sync += [
  16                 If(self.dut.we & self.dut.writable,
  17                     self.dut.din[:32].eq(self.dut.din[:32] + 1),
  18                     self.dut.din[32:].eq(self.dut.din[32:] + 2)
  19                 )
  20             ]
  21
  22     def test_run_sequence(self):
  23         seq = list(range(20))
  24         def gen():
  25             for cycle in count():
  26                 # fire re and we at "random"
  27                 yield self.tb.dut.we.eq(cycle % 2 == 0)
  28                 yield self.tb.dut.re.eq(cycle % 3 == 0)
  29                 # the output if valid must be correct
  30                 if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
  31                     try:
  32                         i = seq.pop(0)
  33                     except IndexError:
  34                         break
  35                     self.assertEqual((yield self.tb.dut.dout[:32]), i)
  36                     self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
  37                 yield
  38         self.run_with(gen())