1 from abc
import abstractproperty
4 from ..lib
.cdc
import ResetSynchronizer
8 __all__
= ["QuicklogicPlatform"]
11 class QuicklogicPlatform(TemplatedPlatform
):
21 * ``symbiflow_write_fasm``
22 * ``symbiflow_write_bitstream``
24 The environment is populated by running the script specified in the environment variable
25 ``NMIGEN_ENV_QLSymbiflow``, if present.
28 * ``add_constraints``: inserts commands in XDC file.
31 device
= abstractproperty()
32 package
= abstractproperty()
34 # Since the QuickLogic version of SymbiFlow toolchain is not upstreamed yet
35 # we should distinguish the QuickLogic version from mainline one.
36 # QuickLogic toolchain: https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/releases
37 toolchain
= "QLSymbiflow"
44 "symbiflow_write_fasm",
45 "symbiflow_write_bitstream"
48 **TemplatedPlatform
.build_script_templates
,
50 /* {{autogenerated}} */
53 "{{name}}.debug.v": r
"""
54 /* {{autogenerated}} */
55 {{emit_debug_verilog()}}
59 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
60 set_io {{port_name}} {{pin_name}}
65 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
66 {% for attr_name, attr_value in attrs.items() -%}
67 set_property {{attr_name}} {{attr_value}} [get_ports {{port_name|tcl_escape}} }]
70 {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
74 {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
75 {% if port_signal is not none -%}
76 create_clock -period {{100000000/frequency}} {{port_signal.name|ascii_escape}}
83 {{invoke_tool("symbiflow_synth")}}
85 -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
86 -d {{platform.device}}
88 -P {{platform.package}}
92 {{invoke_tool("symbiflow_pack")}}
94 -d {{platform.device}}
98 {{invoke_tool("symbiflow_place")}}
100 -d {{platform.device}}
103 -P {{platform.package}}
107 {{invoke_tool("symbiflow_route")}}
109 -d {{platform.device}}
113 {{invoke_tool("symbiflow_write_fasm")}}
115 -d {{platform.device}}
119 {{invoke_tool("symbiflow_write_bitstream")}}
121 -d {{platform.device}}
122 -P {{platform.package}}
132 def add_clock_constraint(self
, clock
, frequency
):
133 super().add_clock_constraint(clock
, frequency
)
134 clock
.attrs
["keep"] = "TRUE"
136 def create_missing_domain(self
, name
):
137 if name
== "sync" and self
.default_clk
is not None:
139 if self
.default_clk
== "sys_clk0":
142 m
.submodules
+= Instance("qlal4s3b_cell_macro",
144 m
.submodules
+= Instance("gclkbuff",
148 clk_i
= self
.request(self
.default_clk
).i
150 if self
.default_rst
is not None:
151 rst_i
= self
.request(self
.default_rst
).i
155 m
.domains
+= ClockDomain("sync")
156 m
.d
.comb
+= ClockSignal("sync").eq(clk_i
)
157 m
.submodules
.reset_sync
= ResetSynchronizer(rst_i
, domain
="sync")