nmigen_boards/arty_a7.py

   1 import os
   2 import subprocess
   3
   4 from nmigen.build import *
   5 from nmigen.vendor.xilinx_7series import *
   6 from .dev import *
   7
   8
   9 __all__ = ["ArtyA7Platform"]
  10
  11
  12 class ArtyA7Platform(Xilinx7SeriesPlatform):
  13     device      = "xc7a35ti"
  14     package     = "csg324"
  15     speed       = "1L"
  16     default_clk = "clk100"
  17     resources   = [
  18         Resource("clk100", 0, Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
  19
  20         Resource("user_led", 0, Pins("H5",  dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  21         Resource("user_led", 1, Pins("J5",  dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  22         Resource("user_led", 2, Pins("T9",  dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  23         Resource("user_led", 3, Pins("T10", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  24
  25         Resource("rgb_led", 0,
  26             Subsignal("r", Pins("G6", dir="o")),
  27             Subsignal("g", Pins("F6", dir="o")),
  28             Subsignal("b", Pins("E1", dir="o")),
  29             Attrs(IOSTANDARD="LVCMOS33")
  30         ),
  31
  32         Resource("rgb_led", 1,
  33             Subsignal("r", Pins("G3", dir="o")),
  34             Subsignal("g", Pins("J4", dir="o")),
  35             Subsignal("b", Pins("G4", dir="o")),
  36             Attrs(IOSTANDARD="LVCMOS33")
  37         ),
  38
  39         Resource("rgb_led", 2,
  40             Subsignal("r", Pins("J3", dir="o")),
  41             Subsignal("g", Pins("J2", dir="o")),
  42             Subsignal("b", Pins("H4", dir="o")),
  43             Attrs(IOSTANDARD="LVCMOS33")
  44         ),
  45
  46         Resource("rgb_led", 3,
  47             Subsignal("r", Pins("K1", dir="o")),
  48             Subsignal("g", Pins("H6", dir="o")),
  49             Subsignal("b", Pins("K2", dir="o")),
  50             Attrs(IOSTANDARD="LVCMOS33")
  51         ),
  52
  53         Resource("user_sw", 0, Pins("A8" , dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  54         Resource("user_sw", 1, Pins("C11", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  55         Resource("user_sw", 2, Pins("C10", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  56         Resource("user_sw", 3, Pins("A10", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  57
  58         Resource("user_btn", 0, Pins("D9", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  59         Resource("user_btn", 1, Pins("C9", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  60         Resource("user_btn", 2, Pins("B9", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  61         Resource("user_btn", 3, Pins("B8", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  62
  63         UARTResource(0,
  64             rx="A9", tx="D10",
  65             attrs=Attrs(IOSTANDARD="LVCMOS33")
  66         ),
  67
  68         Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  69
  70         SPIResource(0,
  71             cs="C1", clk="F1", mosi="H1", miso="G1",
  72             attrs=Attrs(IOSTANDARD="LVCMOS33")
  73         ),
  74
  75         Resource("i2c", 0,
  76             Subsignal("scl",        Pins("L18", dir="io")),
  77             Subsignal("sda",        Pins("M18", dir="io")),
  78             Subsignal("scl_pullup", Pins("A14", dir="o")),
  79             Subsignal("sda_pullup", Pins("A13", dir="o")),
  80             Attrs(IOSTANDARD="LVCMOS33")
  81         ),
  82
  83         *SPIFlashResources(0,
  84             cs="L13", clk="L16", mosi="K17", miso="K18", wp="L14", hold="M14",
  85             attrs=Attrs(IOSTANDARD="LVCMOS33")
  86         ),
  87
  88         Resource("ddr3", 0,
  89             Subsignal("rst",    PinsN("K6", dir="o")),
  90             Subsignal("clk",    DiffPairs("U9", "V9", dir="o"), Attrs(IOSTANDARD="DIFF_SSTL135")),
  91             Subsignal("clk_en", Pins("N5", dir="o")),
  92             Subsignal("cs",     PinsN("U8", dir="o")),
  93             Subsignal("we",     PinsN("P5", dir="o")),
  94             Subsignal("ras",    PinsN("P3", dir="o")),
  95             Subsignal("cas",    PinsN("M4", dir="o")),
  96             Subsignal("a",      Pins("R2 M6 N4 T1 N6 R7 V6 U7 R8 V7 R6 U6 T6 T8", dir="o")),
  97             Subsignal("ba",     Pins("R1 P4 P2", dir="o")),
  98             Subsignal("dqs",    DiffPairs("N2 U2", "N1 V2", dir="io"),
  99                                 Attrs(IOSTANDARD="DIFF_SSTL135")),
 100             Subsignal("dq",     Pins("K5 L3 K3 L6 M3 M1 L4 M2 V4 T5 U4 V5 V1 T3 U3 R3", dir="io"),
 101                                 Attrs(IN_TERM="UNTUNED_SPLIT_40")),
 102             Subsignal("dm",     Pins("L1 U1", dir="o")),
 103             Subsignal("odt",    Pins("R5", dir="o")),
 104             Attrs(IOSTANDARD="SSTL135", SLEW="FAST"),
 105         ),
 106
 107         Resource("eth_clk25", 0, Pins("G18", dir="o"),
 108                  Clock(25e6), Attrs(IOSTANDARD="LVCMOS33")),
 109         Resource("eth_clk50", 0, Pins("G18", dir="o"),
 110                  Clock(50e6), Attrs(IOSTANDARD="LVCMOS33")),
 111         Resource("eth_mii", 0,
 112             Subsignal("rst",     PinsN("C16", dir="o")),
 113             Subsignal("mdio",    Pins("K13", dir="io")),
 114             Subsignal("mdc",     Pins("F16", dir="o")),
 115             Subsignal("tx_clk",  Pins("H16", dir="i")),
 116             Subsignal("tx_en",   Pins("H15", dir="o")),
 117             Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")),
 118             Subsignal("rx_clk",  Pins("F15", dir="i")),
 119             Subsignal("rx_dv",   Pins("G16", dir="i"), Attrs(PULLDOWN="TRUE")), # strap to select MII
 120             Subsignal("rx_er",   Pins("C17", dir="i")),
 121             Subsignal("rx_data", Pins("D18 E17 E18 G17", dir="i")),
 122             Subsignal("col",     Pins("D17", dir="i")),
 123             Subsignal("crs",     Pins("G14", dir="i")),
 124             Attrs(IOSTANDARD="LVCMOS33")
 125         ),
 126         Resource("eth_rmii", 0,
 127             Subsignal("rst",       PinsN("C16", dir="o")),
 128             Subsignal("mdio",      Pins("K13", dir="io")),
 129             Subsignal("mdc",       Pins("F16", dir="o")),
 130             Subsignal("tx_en",     Pins("H15", dir="o")),
 131             Subsignal("tx_data",   Pins("H14 J14", dir="o")),
 132             Subsignal("rx_crs_dv", Pins("G14", dir="i")),
 133             Subsignal("rx_dv",     Pins("G16", dir="i"), Attrs(PULLUP="TRUE")), # strap to select RMII
 134             Subsignal("rx_er",     Pins("C17", dir="i")),
 135             Subsignal("rx_data",   Pins("D18 E17", dir="i")),
 136             Attrs(IOSTANDARD="LVCMOS33")
 137         )
 138     ]
 139     connectors  = [
 140         Connector("pmod", 0, "G13 B11 A11 D12 - - D13 B18 A18 K16 - -"), # JA
 141         Connector("pmod", 1, "E15 E16 D15 C15 - - J17 J18 K15 J15 - -"), # JB
 142         Connector("pmod", 2, "U12 V12 V10 V11 - - U14 V14 T13 U13 - -"), # JC
 143         Connector("pmod", 3, " D4  D3  F4  F3 - -  E2  D2  H2  G2 - -"), # JD
 144
 145         Connector("ck_io", 0, {
 146             # Outer Digital Header
 147             "io0":  "V15",
 148             "io1":  "U16",
 149             "io2":  "P14",
 150             "io3":  "T11",
 151             "io4":  "R12",
 152             "io5":  "T14",
 153             "io6":  "T15",
 154             "io7":  "T16",
 155             "io8":  "N15",
 156             "io9":  "M16",
 157             "io10": "V17",
 158             "io11": "U18",
 159             "io12": "R17",
 160             "io13": "P17",
 161
 162             # Inner Digital Header
 163             "io26": "U11",
 164             "io27": "V16",
 165             "io28": "M13",
 166             "io29": "R10",
 167             "io30": "R11",
 168             "io31": "R13",
 169             "io32": "R15",
 170             "io33": "P15",
 171             "io34": "R16",
 172             "io35": "N16",
 173             "io36": "N14",
 174             "io37": "U17",
 175             "io38": "T18",
 176             "io39": "R18",
 177             "io40": "P18",
 178             "io41": "N17",
 179
 180             # Outer Analog Header as Digital IO
 181             "a0": "F5",
 182             "a1": "D8",
 183             "a2": "C7",
 184             "a3": "E7",
 185             "a4": "D7",
 186             "a5": "D5",
 187
 188             # Inner Analog Header as Digital IO
 189             "io20": "B7",
 190             "io21": "B6",
 191             "io22": "E6",
 192             "io23": "E5",
 193             "io24": "A4",
 194             "io25": "A3"
 195         }),
 196         Connector("xadc", 0, {
 197             # Outer Analog Header
 198             "vaux4_n":   "C5",
 199             "vaux4_p":   "C6",
 200             "vaux5_n":   "A5",
 201             "vaux5_p":   "A6",
 202             "vaux6_n":   "B4",
 203             "vaux6_p":   "C4",
 204             "vaux7_n":   "A1",
 205             "vaux7_p":   "B1",
 206             "vaux15_n":  "B2",
 207             "vaux15_p":  "B3",
 208             "vaux0_n":  "C14",
 209             "vaux0_p":  "D14",
 210
 211             # Inner Analog Header
 212             "vaux12_n": "B7",
 213             "vaux12_p": "B6",
 214             "vaux13_n": "E6",
 215             "vaux13_p": "E5",
 216             "vaux14_n": "A4",
 217             "vaux14_p": "A3",
 218
 219             # Power Measurements
 220             "vsnsuv_n":   "B17",
 221             "vsnsuv_p":   "B16",
 222             "vsns5v0_n":  "B12",
 223             "vsns5v0_p":  "C12",
 224             "isns5v0_n":  "F14",
 225             "isns5v0_n":  "F13",
 226             "isns0v95_n": "A16",
 227             "isns0v95_n": "A15",
 228         })
 229     ]
 230
 231     def toolchain_prepare(self, fragment, name, **kwargs):
 232         overrides = {
 233             "script_before_bitstream":
 234                 "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
 235             "script_after_bitstream":
 236                 "write_cfgmem -force -format bin -interface spix4 -size 16 "
 237                 "-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
 238             "add_constraints":
 239                 "set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
 240         }
 241         return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
 242
 243     def toolchain_program(self, products, name):
 244         xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
 245         with products.extract("{}.bit".format(name)) as bitstream_filename:
 246             subprocess.run([xc3sprog, "-c", "nexys4", bitstream_filename], check=True)
 247
 248
 249 if __name__ == "__main__":
 250     from ._blinky import Blinky
 251     ArtyA7Platform().build(Blinky(), do_program=True)