openpower/isa/bitmanip.mdwn

   1 <!-- Draft Instructions here described in -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- These instructions are *not yet official* -->
   4
   5 # Gather instruction
   6
   7 X-Form
   8
   9 * gbbd RT,RA
  10
  11 Pseudo-code:
  12
  13     result <- [0] * 64
  14     do j = 0 to 7
  15         do k = 0 to 7
  16             b <- (RA)[k*8+j]
  17             result[j*8+k] <- b
  18     RT <- result
  19
  20 Special Registers Altered:
  21
  22     CR0                    (if Rc=1)
  23
  24 # Ternary Bitwise Logic Immediate
  25
  26 TLI-Form
  27
  28 * ternlogi RT,RA,RB,TLI (Rc=0)
  29 * ternlogi. RT,RA,RB,TLI (Rc=1)
  30
  31 Pseudo-code:
  32
  33     result <- [0] * XLEN
  34     do i = 0 to XLEN - 1
  35       idx <- (RT)[i] || (RA)[i] || (RB)[i]
  36       result[i] <- TLI[7-idx]
  37     RT <- result
  38
  39 Special Registers Altered:
  40
  41     CR0                    (if Rc=1)
  42
  43 # GPR Dynamic Binary Logic
  44
  45 BM2-Form
  46
  47 * binlog RT,RA,RB,RC,nh
  48
  49 Pseudo-code:
  50
  51     if nh = 1 then lut <- (RC)[56:59]
  52     else           lut <- (RC)[60:63]
  53     result <- [0] * 64
  54     do i = 0 to 63
  55       idx <- (RA)[i] || (RB)[i]
  56       result[i] <- lut[3-idx]
  57     RT <- result
  58
  59 Description:
  60
  61     If nh contains a 0, let lut be the four LSBs of RC
  62     (bits 60 to 63).  Otherwise let lut be the next
  63     four LSBs of RC (bits 56 to 59).
  64
  65     Let j be the value of the concatenation of the
  66     contents of bit i of RT with bit i of RB.
  67
  68     The value of bit j of lut is placed into bit i of RT.
  69
  70 Special registers altered:
  71
  72     None
  73
  74 # Condition Register Ternary Bitwise Logic Immediate
  75
  76 CRB-Form
  77
  78 * crternlogi BF,BFA,BFB,TLI,msk
  79
  80 Pseudo-code:
  81
  82     bf <- CR[4*BF+32:4*BF+35]
  83     bfa <- CR[4*BFA+32:4*BFA+35]
  84     bfb <- CR[4*BFB+32:4*BFB+35]
  85
  86     result <- [0] * 4
  87     do i = 0 to 3
  88       idx <- bf[i] || bfa[i] || bfb[i]
  89       result[i] <- TLI[7-idx]
  90     do i = 0 to 3
  91         if msk[i] = 1 then
  92             CR[4*BF+32+i] <- result[i]
  93
  94 Special Registers Altered:
  95
  96      CR field BF
  97
  98 # Condition Register Field Dynamic Binary Logic
  99
 100 CRB-Form
 101
 102 * crbinlog BF,BFA,BFB,msk
 103
 104 Pseudo-code:
 105
 106     a <- CR[4*BF+32:4*BFA+35]
 107     b <- CR[4*BFA+32:4*BFA+35]
 108     lut <- CR[4*BFB+32:4*BFB+35]
 109
 110     result <- [0] * 4
 111     do i = 0 to 3
 112       idx <- a[i] || b[i]
 113       result[i] <- lut[3-idx]
 114     do i = 0 to 3
 115         if msk[i] = 1 then
 116             CR[4*BF+32+i] <- result[i]
 117
 118 Description:
 119
 120     For each integer value i, 0 to 3, do the following.
 121
 122     Let j be the value of the concatenation of the
 123     contents of bit i of CR Field BF with bit i of CR Field BFA.
 124
 125     If bit i of msk is set to 1 then the value of bit j of
 126     CR Field BFB is placed into bit i of CR Field BF.
 127
 128     Otherwise, if bit i of msk is a zero then bit i of
 129     CR Field BF is unchanged.
 130
 131     If `msk` is zero an Illegal Instruction trap is raised.
 132
 133 Special registers altered:
 134
 135     CR field BF
 136
 137 # Add With Shift By Immediate
 138
 139 Z23-Form
 140
 141 * sadd RT,RA,RB,SH (Rc=0)
 142 * sadd. RT,RA,RB,SH (Rc=1)
 143
 144 Pseudo-code:
 145
 146     n <- (RB)
 147     m <- ((0b0 || SH) + 1)
 148     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 149
 150 Special Registers Altered:
 151
 152     CR0                    (if Rc=1)
 153
 154 # Add With Shift By Immediate Word
 155
 156 Z23-Form
 157
 158 * saddw RT,RA,RB,SH (Rc=0)
 159 * saddw. RT,RA,RB,SH (Rc=1)
 160
 161 Pseudo-code:
 162
 163     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
 164     if (RB)[XLEN/2] = 1 then
 165         n[0:XLEN/2-1] <- [1]*(XLEN/2)
 166     m <- ((0b0 || SH) + 1)
 167     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 168
 169 Special Registers Altered:
 170
 171     CR0                    (if Rc=1)
 172
 173 # Add With Shift By Immediate Unsigned Word
 174
 175 Z23-Form
 176
 177 * sadduw RT,RA,RB,SH (Rc=0)
 178 * sadduw. RT,RA,RB,SH (Rc=1)
 179
 180 Pseudo-code:
 181
 182     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
 183     m <- ((0b0 || SH) + 1)
 184     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 185
 186 Special Registers Altered:
 187
 188     CR0                    (if Rc=1)