openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     RT <- (RA|0) + EXTS(SI)
  10
  11 Special Registers Altered:
  12
  13     None
  14
  15 # Add Immediate Shifted
  16
  17 D-Form
  18
  19 * addis RT,RA,SI
  20
  21 Pseudo-code:
  22
  23     RT <- (RA|0) + EXTS(SI || [0]*16)
  24
  25 Special Registers Altered:
  26
  27     None
  28
  29 # Add PC Immediate Shifted
  30
  31 DX-Form
  32
  33 * addpcis RT,D
  34
  35 Pseudo-code:
  36
  37     D <- d0||d1||d2
  38     RT <- NIA + EXTS(D || [0]*16)
  39
  40 Special Registers Altered:
  41
  42     None
  43
  44 # Add
  45
  46 XO-Form
  47
  48 * add RT,RA,RB (OE=0 Rc=0)
  49 * add.  RT,RA,RB (OE=0 Rc=1)
  50 * addo RT,RA,RB (OE=1 Rc=0)
  51 * addo.  RT,RA,RB (OE=1 Rc=1)
  52
  53 Pseudo-code:
  54
  55     RT <- (RA) + (RB)
  56
  57 Special Registers Altered:
  58
  59     CR0                     (if Rc=1)
  60     SO OV OV32             (if OE=1)
  61
  62 # Subtract From
  63
  64 XO-Form
  65
  66 * subf RT,RA,RB (OE=0 Rc=0)
  67 * subf.  RT,RA,RB (OE=0 Rc=1)
  68 * subfo RT,RA,RB (OE=1 Rc=0)
  69 * subfo.  RT,RA,RB (OE=1 Rc=1)
  70
  71 Pseudo-code:
  72
  73     RT <- ¬(RA) + (RB) + 1
  74
  75 Special Registers Altered:
  76
  77     CR0                     (if Rc=1)
  78     SO OV OV32             (if OE=1)
  79
  80 # Add Immediate Carrying
  81
  82 D-Form
  83
  84 * addic RT,RA,SI
  85
  86 Pseudo-code:
  87
  88     RT <- (RA) + EXTS(SI)
  89
  90 Special Registers Altered:
  91
  92     CA CA32
  93
  94 # Add Immediate Carrying and Record
  95
  96 D-Form
  97
  98 * addic. RT,RA,SI
  99
 100 Pseudo-code:
 101
 102     RT <- (RA) + EXTS(SI)
 103
 104 Special Registers Altered:
 105
 106     CR0 CA CA32
 107
 108 # Subtract From Immediate Carrying
 109
 110 D-Form
 111
 112 * subfic RT,RA,SI
 113
 114 Pseudo-code:
 115
 116     RT <- ¬(RA) + EXTS(SI) + 1
 117
 118 Special Registers Altered:
 119
 120     CA CA32
 121
 122 # Add Carrying
 123
 124 XO-Form
 125
 126 * addc RT,RA,RB (OE=0 Rc=0)
 127 * addc.  RT,RA,RB (OE=0 Rc=1)
 128 * addco RT,RA,RB (OE=1 Rc=0)
 129 * addco.  RT,RA,RB (OE=1 Rc=1)
 130
 131 Pseudo-code:
 132
 133     RT <- (RA) + (RB)
 134
 135 Special Registers Altered:
 136
 137     CA CA32
 138     CR0                     (if Rc=1)
 139     SO OV OV32             (if OE=1)
 140
 141 # Subtract From Carrying
 142
 143 XO-Form
 144
 145 * subfc RT,RA,RB (OE=0 Rc=0)
 146 * subfc.  RT,RA,RB (OE=0 Rc=1)
 147 * subfco RT,RA,RB (OE=1 Rc=0)
 148 * subfco.  RT,RA,RB (OE=1 Rc=1)
 149
 150 Pseudo-code:
 151
 152     RT <- ¬(RA) + (RB) + 1
 153
 154 Special Registers Altered:
 155
 156     CA CA32
 157     CR0                     (if Rc=1)
 158     SO OV OV32             (if OE=1)
 159
 160 # Add Extended
 161
 162 XO-Form
 163
 164 * adde RT,RA,RB (OE=0 Rc=0)
 165 * adde.  RT,RA,RB (OE=0 Rc=1)
 166 * addeo RT,RA,RB (OE=1 Rc=0)
 167 * addeo.  RT,RA,RB (OE=1 Rc=1)
 168
 169 Pseudo-code:
 170
 171     RT <- (RA) + (RB) + CA
 172
 173 Special Registers Altered:
 174
 175     CA CA32
 176     CR0                     (if Rc=1)
 177     SO OV OV32             (if OE=1)
 178
 179 # Subtract From Extended
 180
 181 XO-Form
 182
 183 * subfe RT,RA,RB (OE=0 Rc=0)
 184 * subfe.  RT,RA,RB (OE=0 Rc=1)
 185 * subfeo RT,RA,RB (OE=1 Rc=0)
 186 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 187
 188 Pseudo-code:
 189
 190     RT <- ¬(RA) + (RB) + CA
 191
 192 Special Registers Altered:
 193
 194     CA CA32
 195     CR0                     (if Rc=1)
 196     SO OV OV32             (if OE=1)
 197
 198 # Add to Minus One Extended
 199
 200 XO-Form
 201
 202 * addme RT,RA (OE=0 Rc=0)
 203 * addme.  RT,RA (OE=0 Rc=1)
 204 * addmeo RT,RA (OE=1 Rc=0)
 205 * addmeo.  RT,RA (OE=1 Rc=1)
 206
 207 Pseudo-code:
 208
 209     RT <- (RA) + CA - 1
 210
 211 Special Registers Altered:
 212
 213     CA CA32
 214     CR0                     (if Rc=1)
 215     SO OV OV32             (if OE=1)
 216
 217 # Subtract From Minus One Extended
 218
 219 XO-Form
 220
 221 * subfme RT,RA (OE=0 Rc=0)
 222 * subfme.  RT,RA (OE=0 Rc=1)
 223 * subfmeo RT,RA (OE=1 Rc=0)
 224 * subfmeo.  RT,RA (OE=1 Rc=1)
 225
 226 Pseudo-code:
 227
 228     RT <- ¬(RA) + CA - 1
 229
 230 Special Registers Altered:
 231
 232     CA CA32
 233     CR0                     (if Rc=1)
 234     SO OV OV32             (if OE=1)
 235
 236 # Add Extended using alternate carry bit
 237
 238 Z23-Form
 239
 240 * addex RT,RA,RB,CY
 241
 242 Pseudo-code:
 243
 244     if CY=0 then RT <- (RA) + (RB) + OV
 245
 246 Special Registers Altered:
 247
 248     OV OV32                (if CY=0 )
 249
 250 # Subtract From Zero Extended
 251
 252 XO-Form
 253
 254 * subfze RT,RA (OE=0 Rc=0)
 255 * subfze.  RT,RA (OE=0 Rc=1)
 256 * subfzeo RT,RA (OE=1 Rc=0)
 257 * subfzeo.  RT,RA (OE=1 Rc=1)
 258
 259 Pseudo-code:
 260
 261     RT <- ¬(RA) + CA
 262
 263 Special Registers Altered:
 264
 265     CA CA32
 266     CR0                     (if Rc=1)
 267     SO OV OV32             (if OE=1)
 268
 269 # Add to Zero Extended
 270
 271 XO-Form
 272
 273 * addze RT,RA (OE=0 Rc=0)
 274 * addze.  RT,RA (OE=0 Rc=1)
 275 * addzeo RT,RA (OE=1 Rc=0)
 276 * addzeo.  RT,RA (OE=1 Rc=1)
 277
 278 Pseudo-code:
 279
 280     RT <- (RA) + CA
 281
 282 Special Registers Altered:
 283
 284     CA CA32
 285     CR0                     (if Rc=1)
 286     SO OV OV32             (if OE=1)
 287
 288 # Negate
 289
 290 XO-Form
 291
 292 * neg RT,RA (OE=0 Rc=0)
 293 * neg.  RT,RA (OE=0 Rc=1)
 294 * nego RT,RA (OE=1 Rc=0)
 295 * nego.  RT,RA (OE=1 Rc=1)
 296
 297 Pseudo-code:
 298
 299     RT <- ¬(RA) + 1
 300
 301 Special Registers Altered:
 302
 303     CR0                     (if Rc=1)
 304     SO OV OV32             (if OE=1)
 305
 306 # Multiply Low Immediate
 307
 308 D-Form
 309
 310 * mulli RT,RA,SI
 311
 312 Pseudo-code:
 313
 314     prod[0:127] <- MULS((RA), EXTS(SI))
 315     RT <- prod[64:127]
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Multiply High Word
 322
 323 XO-Form
 324
 325 * mulhw RT,RA,RB (Rc=0)
 326 * mulhw.  RT,RA,RB (Rc=1)
 327
 328 Pseudo-code:
 329
 330     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 331     RT[32:63] <- prod[0:31]
 332     RT[0:31] <- prod[0:31]
 333
 334 Special Registers Altered:
 335
 336     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 337
 338 # Multiply Low Word
 339
 340 XO-Form
 341
 342 * mullw RT,RA,RB (OE=0 Rc=0)
 343 * mullw.  RT,RA,RB (OE=0 Rc=1)
 344 * mullwo RT,RA,RB (OE=1 Rc=0)
 345 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 346
 347 Pseudo-code:
 348
 349     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 350     RT <- prod
 351     overflow <- ((prod[0:32] != [0]*33) &
 352                  (prod[0:32] != [1]*33))
 353
 354 Special Registers Altered:
 355
 356     CR0                     (if Rc=1)
 357     SO OV OV32             (if OE=1)
 358
 359 # Multiply High Word Unsigned
 360
 361 XO-Form
 362
 363 * mulhwu RT,RA,RB (Rc=0)
 364 * mulhwu.  RT,RA,RB (Rc=1)
 365
 366 Pseudo-code:
 367
 368     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 369     RT[32:63] <- prod[0:31]
 370     RT[0:31] <- prod[0:31]
 371
 372 Special Registers Altered:
 373
 374     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 375
 376 # Divide Word
 377
 378 XO-Form
 379
 380 * divw RT,RA,RB (OE=0 Rc=0)
 381 * divw.  RT,RA,RB (OE=0 Rc=1)
 382 * divwo RT,RA,RB (OE=1 Rc=0)
 383 * divwo.  RT,RA,RB (OE=1 Rc=1)
 384
 385 Pseudo-code:
 386
 387     dividend[0:31] <-  (RA)[32:63]
 388     divisor[0:31] <- (RB) [32:63]
 389     if (((dividend = 0x8000_0000) &
 390          (divisor = 0xffff_ffff)) |
 391          (divisor = 0x0000_0000)) then
 392         RT[0:63] <- undefined[0:63]
 393         overflow <- 1
 394     else
 395         RT[32:63] <- DIVS(dividend, divisor)
 396         RT[0:31] <- undefined[0:31]
 397         overflow <- 0
 398
 399 Special Registers Altered:
 400
 401     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 402     SO OV OV32                              (if OE=1)
 403
 404 # Divide Word Unsigned
 405
 406 XO-Form
 407
 408 * divwu RT,RA,RB (OE=0 Rc=0)
 409 * divwu.  RT,RA,RB (OE=0 Rc=1)
 410 * divwuo RT,RA,RB (OE=1 Rc=0)
 411 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 412
 413 Pseudo-code:
 414
 415     dividend[0:31] <- (RA)[32:63]
 416     divisor[0:31] <- (RB)[32:63]
 417     if divisor != 0 then
 418         RT[32:63] <-  dividend / divisor
 419         RT[0:31] <- undefined[0:31]
 420         overflow <- 0
 421     else
 422         RT[0:63] <- undefined[0:63]
 423         overflow <- 1
 424
 425 Special Registers Altered:
 426
 427     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 428     SO OV OV32                              (if OE=1)
 429
 430 # Divide Word Extended
 431
 432 XO-Form
 433
 434 * divwe RT,RA,RB (OE=0 Rc=0)
 435 * divwe.  RT,RA,RB (OE=0 Rc=1)
 436 * divweo RT,RA,RB (OE=1 Rc=0)
 437 * divweo.  RT,RA,RB (OE=1 Rc=1)
 438
 439 Pseudo-code:
 440
 441     dividend[0:63] <- (RA)[32:63] || [0]*32
 442     divisor[0:63] <- [0]*32 || (RB)[32:63]
 443     if (divisor = 0x0000_0000_0000_0000) then
 444         overflow <- 1
 445     else
 446         result <- DIVS(dividend, divisor)
 447         if (result[32:63] = 0) then
 448             RT[32:63] <- result[0:31]
 449             RT[0:31] <- undefined[0:31]
 450             overflow <- 0
 451         else
 452             overflow <- 1
 453     if overflow = 1 then
 454         RT[0:63] <- undefined[0:63]
 455
 456 Special Registers Altered:
 457
 458     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 459     SO OV OV32                              (if OE=1)
 460
 461 # Divide Word Extended Unsigned
 462
 463 XO-Form
 464
 465 * divweu RT,RA,RB (OE=0 Rc=0)
 466 * divweu.  RT,RA,RB (OE=0 Rc=1)
 467 * divweuo RT,RA,RB (OE=1 Rc=0)
 468 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 469
 470 Pseudo-code:
 471
 472     dividend[0:63] <- (RA)[32:63] || [0]*32
 473     divisor[0:63] <- [0]*32 || (RB)[32:63]
 474     if (divisor = 0x0000_0000_0000_0000) then
 475         overflow <- 1
 476     else
 477         result <- dividend /  divisor
 478         if (RA) < (RB) then
 479             RT[32:63] <- result[0:31]
 480             RT[0:31] <- undefined[0:31]
 481             overflow <- 0
 482         else
 483             overflow <- 1
 484     if overflow = 1 then
 485         RT[0:63] <- undefined[0:63]
 486
 487 Special Registers Altered:
 488
 489     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 490     SO OV OV32                              (if OE=1)
 491
 492 # Modulo Signed Word
 493
 494 X-Form
 495
 496 * modsw RT,RA,RB
 497
 498 Pseudo-code:
 499
 500     dividend[0:31] <- (RA)[32:63]
 501     divisor [0:31] <- (RB)[32:63]
 502     if (((dividend = 0x8000_0000) &
 503          (divisor = 0xffff_ffff)) |
 504          (divisor = 0x0000_0000)) then
 505         RT[0:63] <- undefined[0:63]
 506         overflow <- 1
 507     else
 508         RT[32:63] <- MODS(dividend, divisor)
 509         RT[0:31] <- undefined[0:31]
 510         overflow <- 0
 511
 512 Special Registers Altered:
 513
 514     None
 515
 516 # Modulo Unsigned Word
 517
 518 X-Form
 519
 520 * moduw RT,RA,RB
 521
 522 Pseudo-code:
 523
 524     dividend[0:31] <- (RA) [32:63]
 525     divisor [0:31] <- (RB) [32:63]
 526     if divisor = 0x0000_0000 then
 527         RT[0:63] <- undefined[0:63]
 528         overflow <- 1
 529     else
 530         RT[32:63] <- MODS(dividend, divisor)
 531         RT[0:31] <- undefined[0:31]
 532         overflow <- 0
 533
 534 Special Registers Altered:
 535
 536     None
 537
 538 # Deliver A Random Number
 539
 540 X-Form
 541
 542 * darn RT,L
 543
 544 Pseudo-code:
 545
 546     RT <- random(L)
 547
 548 Special Registers Altered:
 549
 550     none
 551
 552 # Multiply Low Doubleword
 553
 554 XO-Form
 555
 556 * mulld RT,RA,RB (OE=0 Rc=0)
 557 * mulld.  RT,RA,RB (OE=0 Rc=1)
 558 * mulldo RT,RA,RB (OE=1 Rc=0)
 559 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 560
 561 Pseudo-code:
 562
 563     prod[0:127] <- MULS((RA), (RB))
 564     RT <- prod[64:127]
 565     overflow <- ((prod[0:64] != [0]*65) &
 566                  (prod[0:64] != [1]*65))
 567
 568 Special Registers Altered:
 569
 570     CR0                     (if Rc=1)
 571     SO OV OV32             (if OE=1)
 572
 573 # Multiply High Doubleword
 574
 575 XO-Form
 576
 577 * mulhd RT,RA,RB (Rc=0)
 578 * mulhd.  RT,RA,RB (Rc=1)
 579
 580 Pseudo-code:
 581
 582     prod[0:127] <- MULS((RA), (RB))
 583     RT <- prod[0:63]
 584
 585 Special Registers Altered:
 586
 587     CR0                     (if Rc=1)
 588
 589 # Multiply High Doubleword Unsigned
 590
 591 XO-Form
 592
 593 * mulhdu RT,RA,RB (Rc=0)
 594 * mulhdu.  RT,RA,RB (Rc=1)
 595
 596 Pseudo-code:
 597
 598     prod[0:127] <- (RA) *  (RB)
 599     RT <- prod[0:63]
 600
 601 Special Registers Altered:
 602
 603     CR0                    (if Rc=1)
 604
 605 # Multiply-Add High Doubleword VA-Form
 606
 607 VA-Form
 608
 609 * maddhd RT,RA.RB,RC
 610
 611 Pseudo-code:
 612
 613     prod[0:127] <- MULS((RA), (RB))
 614     sum[0:127] <- prod + EXTS(RC)
 615     RT <- sum[0:63]
 616
 617 Special Registers Altered:
 618
 619     None
 620
 621 # Multiply-Add High Doubleword Unsigned
 622
 623 VA-Form
 624
 625 * maddhdu RT,RA.RB,RC
 626
 627 Pseudo-code:
 628
 629     prod[0:127] <- (RA) * (RB)
 630     sum[0:127] <- prod + EXTZ(RC)
 631     RT <- sum[0:63]
 632
 633 Special Registers Altered:
 634
 635     None
 636
 637 # Multiply-Add Low Doubleword
 638
 639 VA-Form
 640
 641 * maddld RT,RA.RB,RC
 642
 643 Pseudo-code:
 644
 645     prod[0:127] <- MULS((RA), (RB))
 646     sum[0:127] <- prod + EXTS(RC)
 647     RT <- sum[64:127]
 648
 649 Special Registers Altered:
 650
 651     None
 652
 653 # Divide Doubleword
 654
 655 XO-Form
 656
 657 * divd RT,RA,RB (OE=0 Rc=0)
 658 * divd.  RT,RA,RB (OE=0 Rc=1)
 659 * divdo RT,RA,RB (OE=1 Rc=0)
 660 * divdo.  RT,RA,RB (OE=1 Rc=1)
 661
 662 Pseudo-code:
 663
 664     dividend[0:63] <- (RA)
 665     divisor[0:63] <- (RB)
 666     if (((dividend = 0x8000_0000_0000_0000) &
 667          (divisor = 0xffff_ffff_ffff_ffff)) |
 668          (divisor = 0x0000_0000_0000_0000)) then
 669         RT[0:63] <- undefined[0:63]
 670         overflow <- 1
 671     else
 672         RT <- DIVS(dividend, divisor)
 673         overflow <- 0
 674
 675 Special Registers Altered:
 676
 677     CR0                     (if Rc=1)
 678     SO OV OV32             (if OE=1)
 679
 680 # Divide Doubleword Unsigned
 681
 682 XO-Form
 683
 684 * divdu RT,RA,RB (OE=0 Rc=0)
 685 * divdu.  RT,RA,RB (OE=0 Rc=1)
 686 * divduo RT,RA,RB (OE=1 Rc=0)
 687 * divduo.  RT,RA,RB (OE=1 Rc=1)
 688
 689 Pseudo-code:
 690
 691     dividend[0:63] <- (RA)
 692     divisor[0:63] <- (RB)
 693     if (divisor = 0x0000_0000_0000_0000) then
 694         RT[0:63] <- undefined[0:63]
 695         overflow <- 1
 696     else
 697         RT <- dividend / divisor
 698         overflow <- 0
 699
 700 Special Registers Altered:
 701
 702     CR0                     (if Rc=1)
 703     SO OV OV32             (if OE=1)
 704
 705 # Divide Doubleword Extended
 706
 707 XO-Form
 708
 709 * divde RT,RA,RB (OE=0 Rc=0)
 710 * divde.  RT,RA,RB (OE=0 Rc=1)
 711 * divdeo RT,RA,RB (OE=1 Rc=0)
 712 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 713
 714 Pseudo-code:
 715
 716     dividend[0:127] <-  (RA) || [0]*64
 717     divisor[0:127] <- [0]*64 || (RB)
 718     if divisor = [0]*128 then
 719         overflow <- 1
 720     else
 721         result <- DIVS(dividend, divisor)
 722         if result[64:127] = 0x0000_0000_0000_0000 then
 723             RT <- result[63:127]
 724             overflow <- 0
 725         else
 726             overflow <- 1
 727     if overflow = 1 then
 728         RT[0:63] <- undefined[0:63]
 729
 730 Special Registers Altered:
 731
 732     CR0                     (if Rc=1)
 733     SO OV OV32             (if OE=1)
 734
 735 # Divide Doubleword Extended Unsigned
 736
 737 XO-Form
 738
 739 * divdeu RT,RA,RB (OE=0 Rc=0)
 740 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 741 * divdeuo RT,RA,RB (OE=1 Rc=0)
 742 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 743
 744 Pseudo-code:
 745
 746     dividend[0:127] <-  (RA) || [0]*64
 747     divisor[0:127] <- [0]*64 || (RB)
 748     if divisor = [0]*128 then
 749         overflow <- 1
 750     else
 751         result <- dividend /  divisor
 752         if (RA) < (RB) then
 753             RT <- result[63:127]
 754             overflow <- 0
 755         else
 756             overflow <- 1
 757     if overflow = 1 then
 758         RT[0:63] <- undefined[0:63]
 759
 760 Special Registers Altered:
 761
 762     CR0                     (if Rc=1)
 763     SO OV OV32             (if OE=1)
 764
 765 # Modulo Signed Doubleword
 766
 767 X-Form
 768
 769 * modsd RT,RA,RB
 770
 771 Pseudo-code:
 772
 773     dividend <- (RA)
 774     divisor  <- (RB)
 775     if (((dividend = 0x8000_0000_0000_0000) &
 776          (divisor = 0xffff_ffff_ffff_ffff)) |
 777          (divisor = 0x0000_0000_0000_0000)) then
 778         RT[0:63] <- undefined[0:63]
 779         overflow <- 1
 780     else
 781         RT       <- MODS(dividend, divisor)
 782         overflow <- 0
 783
 784 Special Registers Altered:
 785
 786     None
 787
 788 # Modulo Unsigned Doubleword
 789
 790 X-Form
 791
 792 * modud RT,RA,RB
 793
 794 Pseudo-code:
 795
 796     dividend <- (RA)
 797     divisor  <- (RB)
 798     if (divisor = 0x0000_0000_0000_0000) then
 799         RT[0:63] <- undefined[0:63]
 800         overflow <- 1
 801     else
 802         RT       <- dividend % divisor
 803         overflow <- 0
 804
 805 Special Registers Altered:
 806
 807     None
 808