7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
10 * binutils <https://bugs.libre-soc.org/show_bug.cgi?id=836>
11 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
17 pseudocode: [[openpower/isa/bitmanip]]
19 this extension amalgamates bitmanipulation primitives from many sources,
20 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
21 Also included are DSP/Multimedia operations suitable for Audio/Video.
22 Vectorisation and SIMD are removed: these are straight scalar (element)
23 operations making them suitable for embedded applications. Vectorisation
24 Context is provided by [[openpower/sv]].
26 When combined with SV, scalar variants of bitmanip operations found in
27 VSX are added so that the Packed SIMD aspects of VSX may be retired as
28 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
29 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
30 or embedded scenarios.
32 ternlogv is experimental and is the only operation that may be considered
33 a "Packed SIMD". It is added as a variant of the already well-justified
34 ternlog operation (done in AVX512 as an immediate only) "because it
35 looks fun". As it is based on the LUT4 concept it will allow accelerated
36 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
37 achieve similar objectives.
39 general-purpose Galois Field 2^M operations are added so as to avoid
40 huge custom opcode proliferation across many areas of Computer Science.
41 however for convenience and also to avoid setup costs, some of the more
42 common operations (clmul, crc32) are also added. The expectation is
43 that these operations would all be covered by the same pipeline.
45 note that there are brownfield spaces below that could incorporate
46 some of the set-before-first and other scalar operations listed in
48 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
49 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
53 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
54 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
55 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
56 * <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
58 [[!inline pages="openpower/sv/draft_opcode_tables" quick="yes" raw="yes" ]]
60 # binary and ternary bitops
62 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
63 bits from each input, concatenate them and perform a lookup into a
64 table using an 8-8-bit immediate (for the ternary instructions), or in
65 another register (4-bit for the binary instructions). The binary lookup
66 instructions have CR Field lookup variants due to CR Fields being 4 bit.
69 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
74 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
75 | -- | -- | --- | --- | ----- | --- |--|
76 | NN | RT | RA | RB | im0-7 | 00 |Rc|
79 idx = c << 2 | b << 1 | a
80 return imm[idx] # idx by LSB0 order
83 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
87 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
88 lookup table is 4 bits wide not 8 bits, and secondly the lookup
89 table comes from a register not an immediate.
91 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
92 | -- | -- | --- | --- | ----- |--------|---------|
93 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
94 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
96 For binlut, the 4-bit LUT may be selected from either the high nibble
97 or the low nibble of the first byte of RC:
101 return imm[idx] # idx by LSB0 order
103 imm = (RC>>(nh*4))&0b1111
105 RT[i] = lut2(imm, RB[i], RA[i])
107 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
110 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
112 When Vectorised with SVP64, as usual both source and destination may be
115 *Programmer's note: a dynamic ternary lookup may be synthesised from
116 a pair of `binlut` instructions followed by a `ternlogi` to select which
117 to merge. Use `nh` to select which nibble to use as the lookup table
118 from the RC source register (`nh=1` nibble high), i.e. keeping
119 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
124 another mode selection would be CRs not Ints.
128 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
129 |----|----|----|-----|-----|-----|-----|-----|---|
130 | NN | BF | msk|BFA | msk | BFB | TLI | XO |TLI|
133 a,b,c = CRs[BF][i], CRs[BFA][i], CRs[BFB][i])
134 if msk[i] CRs[BF][i] = lut3(imm, a, b, c)
136 This instruction is remarkably similar to the existing crops, `crand` etc.
137 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
138 is the ternary LUT version of crops, having an 8-bit LUT. However it
139 is an overwrite instruction in order to save on register file ports,
140 due to the mask requiring the contents of the BF to be both read and
143 Programmer's note: This instruction is useful when combined with Matrix REMAP
144 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
145 applications in Computer Science.
149 With ternary (LUT3) dynamic instructions being very costly,
150 and CR Fields being only 4 bit, a binary (LUT2) variant is better
154 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
155 |----|----|----|-----|-----|-----|-----|-----|---|
156 | NN | BF | msk|BFA | msk | BFB | // | XO | //|
159 a,b = CRs[BF][i], CRs[BF][i])
160 if msk[i] CRs[BF][i] = lut2(CRs[BFB], a, b)
162 When SVP64 Vectorised any of the 4 operands may be Scalar or
163 Vector, including `BFB` meaning that multiple different dynamic
164 lookups may be performed with a single instruction. Note that
165 this instruction is deliberately an overwrite in order to reduce
166 the number of register file ports required: like `crternlogi`
167 the contents of `BF` **must** be read due to the mask only
168 writing back to non-masked-out bits of `BF`.
170 *Programmer's note: just as with binlut and ternlogi, a pair
171 of crbinlog instructions followed by a merging crternlogi may
172 be deployed to synthesise dynamic ternary (LUT3) CR Field
179 required for the [[sv/av_opcodes]]
181 signed and unsigned min/max for integer. this is sort-of partly
182 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
183 is one of the sources, but not both signed and unsigned. when the dest
184 is also one of the srces and the mv fails due to the CR bittest failing
185 this will only overwrite the dest where the src is greater (or less).
187 signed/unsigned min/max gives more flexibility.
191 * XO=0001001110, itype=0b00 min, unsigned
192 * XO=0101001110, itype=0b01 min, signed
193 * XO=0011001110, itype=0b10 max, unsigned
194 * XO=0111001110, itype=0b11 max, signed
198 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
199 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
201 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
202 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
204 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
205 { return rs1 < rs2 ? rs1 : rs2;
207 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
208 { return rs1 > rs2 ? rs1 : rs2;
214 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
218 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
219 return (rs1 + rs2 + 1) >> 1:
225 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
229 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
230 return (src1 > src2) ? (src1-src2) : (src2-src1)
236 required for the [[sv/av_opcodes]], these are needed for motion estimation.
237 both are overwrite on RS.
240 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
241 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
243 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
244 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
248 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
249 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
250 SVP64 designation from RS-as-dest. This gives a limited range of
251 non-overwrite capability.
253 # shift-and-add <a name="shift-add"> </a>
255 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
256 Too complex to add more LD/ST, a compromise is to add shift-and-add.
257 Replaces a pair of explicit instructions in hot-loops.
261 |0 |6 |11 |15 |16 |21 |23 |31 |
262 | PO | RT | RA | RB |sm | XO |Rc |
269 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
271 Pseudo-code (shadduw):
273 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
275 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
278 uint_xlen_t shadd(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
280 return (RB << (sm+1)) + RA;
283 uint_xlen_t shadduw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
284 uint_xlen_t n = RB & 0xFFFFFFFF;
286 return (n << (sm+1)) + RA;
292 based on RV bitmanip singlebit set, instruction format similar to shift
293 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
294 rldicl but only immediate version). however bitmask-invert is not,
295 and set/clr are not covered, although they can use the same Shift ALU.
297 bmext (RB) version is not the same as rldicl because bmext is a right
298 shift by RC, where rldicl is a left rotate. for the immediate version
299 this does not matter, so a bmexti is not required. bmrev however there
300 is no direct equivalent and consequently a bmrevi is required.
302 bmset (register for mask amount) is particularly useful for creating
303 predicate masks where the length is a dynamic runtime quantity.
304 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
305 in a single instruction without needing to initialise or depend on any
308 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
309 | -- | -- | --- | --- | --- | ------- |--| ----- |
310 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
312 Immediate-variant is an overwrite form:
314 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
315 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
316 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
322 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
323 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
328 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
329 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
330 return mask_a ^ mask_b
333 uint_xlen_t bmset(RS, RB, sh)
335 int shamt = RB & (XLEN - 1);
337 return RS | (mask << shamt);
340 uint_xlen_t bmclr(RS, RB, sh)
342 int shamt = RB & (XLEN - 1);
344 return RS & ~(mask << shamt);
347 uint_xlen_t bminv(RS, RB, sh)
349 int shamt = RB & (XLEN - 1);
351 return RS ^ (mask << shamt);
354 uint_xlen_t bmext(RS, RB, sh)
356 int shamt = RB & (XLEN - 1);
358 return mask & (RS >> shamt);
362 bitmask extract with reverse. can be done by bit-order-inverting all
363 of RB and getting bits of RB from the opposite end.
365 when RA is zero, no shift occurs. this makes bmextrev useful for
366 simply reversing all bits of a register.
370 rev[0:msb] = rb[msb:0];
373 uint_xlen_t bmrevi(RA, RB, sh)
376 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
377 shamt = (XLEN-1)-shamt; # shift other end
378 brb = bitreverse(GPR(RB)) # swap LSB-MSB
380 return mask & (brb >> shamt);
383 uint_xlen_t bmrev(RA, RB, RC) {
384 return bmrevi(RA, RB, GPR(RC) & 0b111111);
388 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
389 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
390 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
392 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
393 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
394 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
396 # grevlut <a name="grevlut"> </a>
398 generalised reverse combined with a pair of LUT2s and allowing
399 a constant `0b0101...0101` when RA=0, and an option to invert
400 (including when RA=0, giving a constant 0b1010...1010 as the
401 initial value) provides a wide range of instructions
402 and a means to set hundreds of regular 64 bit patterns with one
403 single 32 bit instruction.
405 the two LUT2s are applied left-half (when not swapping)
406 and right-half (when swapping) so as to allow a wider
409 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
411 * A value of `0b11001010` for the immediate provides
412 the functionality of a standard "grev".
413 * `0b11101110` provides gorc
415 grevlut should be arranged so as to produce the constants
416 needed to put into bext (bitextract) so as in turn to
417 be able to emulate x86 pmovmask instructions
418 <https://www.felixcloutier.com/x86/pmovmskb>.
419 This only requires 2 instructions (grevlut, bext).
421 Note that if the mask is required to be placed
422 directly into CR Fields (for use as CR Predicate
423 masks rather than a integer mask) then sv.cmpi or sv.ori
424 may be used instead, bearing in mind that sv.ori
425 is a 64-bit instruction, and `VL` must have been
426 set to the required length:
428 sv.ori./elwid=8 r10.v, r10.v, 0
430 The following settings provide the required mask constants:
432 | RA=0 | RB | imm | iv | result |
433 | ------- | ------- | ---------- | -- | ---------- |
434 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
435 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
436 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
437 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
438 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
439 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
441 Better diagram showing the correct ordering of shamt (RB). A LUT2
442 is applied to all locations marked in red using the first 4
443 bits of the immediate, and a separate LUT2 applied to all
444 locations in green using the upper 4 bits of the immediate.
446 <img src="/openpower/sv/grevlut.png" width=700 />
448 demo code [[openpower/sv/grevlut.py]]
453 return imm[idx] # idx by LSB0 order
455 dorow(imm8, step_i, chunksize, us32b):
456 for j in 0 to 31 if is32b else 63:
457 if (j&chunk_size) == 0
461 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
464 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
466 uint64_t x = 0x5555_5555_5555_5555;
467 if (RA != 0) x = GPR(RA);
469 int shamt = RB & 31 if is32b else 63
470 for i in 0 to (6-is32b)
472 if (shamt & step) x = dorow(imm, x, step, is32b)
477 A variant may specify different LUT-pairs per row,
478 using one byte of RB for each. If it is desired that
479 a particular row-crossover shall not be applied it is
480 a simple matter to set the appropriate LUT-pair in RB
481 to effect an identity transform for that row (`0b11001010`).
484 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
486 uint64_t x = 0x5555_5555_5555_5555;
487 if (RA != 0) x = GPR(RA);
489 for i in 0 to (6-is32b)
491 imm = (RB>>(i*8))&0xff
492 x = dorow(imm, x, step, is32b)
498 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
499 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
500 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
501 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
503 An equivalent to `grevlogw` may be synthesised by setting the
504 appropriate bits in RB to set the top half of RT to zero.
505 Thus an explicit grevlogw instruction is not necessary.
509 based on RV bitmanip.
511 RA contains a vector of indices to select parts of RB to be
512 copied to RT. The immediate-variant allows up to an 8 bit
513 pattern (repeated) to be targetted at different parts of RT.
515 xperm shares some similarity with one of the uses of bmator
516 in that xperm indices are binary addressing where bitmator
517 may be considered to be unary addressing.
520 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
523 uint_xlen_t sz = 1LL << sz_log2;
524 uint_xlen_t mask = (1LL << sz) - 1;
525 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
526 for (int i = 0; i < XLEN; i += sz) {
527 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
529 r |= ((RB >> pos) & mask) << i;
533 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
536 uint_xlen_t sz = 1LL << sz_log2;
537 uint_xlen_t mask = (1LL << sz) - 1;
538 for (int i = 0; i < XLEN; i += sz) {
539 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
541 r |= ((RB >> pos) & mask) << i;
545 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
546 { return xperm(RA, RB, 2); }
547 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
548 { return xperm(RA, RB, 3); }
549 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
550 { return xperm(RA, RB, 4); }
551 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
552 { return xperm(RA, RB, 5); }
557 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
558 as GF2P8AFFINEQB. uses:
560 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
561 * SM4, Reed Solomon, RAID6
562 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
563 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
564 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
566 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
567 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
568 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
572 uint64_t bmatflip(uint64_t RA)
581 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
583 uint64_t RAt = bmatflip(RA);
584 uint8_t u[8]; // rows of RS
585 uint8_t v[8]; // cols of RA
586 for (int i = 0; i < 8; i++) {
591 for (int i = 0; i < 64; i++) {
592 bit = (imm >> (i%8)) & 1;
593 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
599 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
600 return bmatxori(RA, RB, 0xff)
603 uint64_t bmator(uint64_t RA, uint64_t RB) {
605 uint64_t RBt = bmatflip(RB);
606 uint8_t u[8]; // rows of RA
607 uint8_t v[8]; // cols of RB
608 for (int i = 0; i < 8; i++) {
613 for (int i = 0; i < 64; i++) {
614 if ((u[i / 8] & v[i % 8]) != 0)
620 uint64_t bmatand(uint64_t RA, uint64_t RB) {
622 uint64_t RBt = bmatflip(RB);
623 uint8_t u[8]; // rows of RA
624 uint8_t v[8]; // cols of RB
625 for (int i = 0; i < 8; i++) {
630 for (int i = 0; i < 64; i++) {
631 if ((u[i / 8] & v[i % 8]) == 0xff)
638 # Introduction to Carry-less and GF arithmetic
640 * obligatory xkcd <https://xkcd.com/2595/>
642 There are three completely separate types of Galois-Field-based arithmetic
643 that we implement which are not well explained even in introductory
644 literature. A slightly oversimplified explanation is followed by more
645 accurate descriptions:
647 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
648 but is accidentally referred to as GF(2) - see below as to why.
649 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
651 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
652 (2^N) and a second "reducing" polynomial (similar to a prime number), these
653 are said to be GF(2^N) arithmetic.
655 further detailed and more precise explanations are provided below
657 * **Polynomials with coefficients in `GF(2)`**
658 (aka. Carry-less arithmetic -- the `cl*` instructions).
659 This isn't actually a Galois Field, but its coefficients are. This is
660 basically binary integer addition, subtraction, and multiplication like
661 usual, except that carries aren't propagated at all, effectively turning
662 both addition and subtraction into the bitwise xor operation. Division and
663 remainder are defined to match how addition and multiplication works.
664 * **Galois Fields with a prime size**
665 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
666 This is basically just the integers mod `p`.
667 * **Galois Fields with a power-of-a-prime size**
668 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
670 We only implement these for `p == 2`, called Binary Galois Fields
671 (`GF(2^n)` -- the `gfb*` instructions).
672 For any prime `p`, `GF(p^n)` is implemented as polynomials with
673 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
674 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
675 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
676 Polynomial must be an irreducable polynomial (like primes, but for
677 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
678 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
679 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
680 polynomials used to implement `GF(p^n)`.
682 Many implementations and much of the literature do not make a clear
683 distinction between these three categories, which makes it confusing
684 to understand what their purpose and value is.
686 * carry-less multiply is extremely common and is used for the ubiquitous
687 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
688 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
689 has significant uses throughout cryptography
690 * GF(p) is the basis again of a significant quantity of algorithms
691 (TODO, list them, jacob knows what they are), even though the
692 modulo is limited to be below 64-bit (size of a scalar int)
694 # Instructions for Carry-less Operations
696 aka. Polynomials with coefficients in `GF(2)`
698 Carry-less addition/subtraction is simply XOR, so a `cladd`
699 instruction is not provided since the `xor[i]` instruction can be used instead.
701 These are operations on polynomials with coefficients in `GF(2)`, with the
702 polynomial's coefficients packed into integers with the following algorithm:
705 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
708 ## Carry-less Multiply Instructions
711 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
712 <https://www.felixcloutier.com/x86/pclmulqdq> and
713 <https://en.m.wikipedia.org/wiki/Carry-less_product>
715 They are worth adding as their own non-overwrite operations
716 (in the same pipeline).
718 ### `clmul` Carry-less Multiply
721 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
724 ### `clmulh` Carry-less Multiply High
727 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
730 ### `clmulr` Carry-less Multiply (Reversed)
732 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
736 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
739 ## `clmadd` Carry-less Multiply-Add
742 clmadd RT, RA, RB, RC
746 (RT) = clmul((RA), (RB)) ^ (RC)
749 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
751 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
752 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
753 to avoid the need for a temp register. RS is written to as well as RT.
755 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
756 definition of the Inverse Discrete Fourier Transform involves calculating a
757 multiplicative inverse, which may not exist in every Ring, therefore the
758 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
759 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
760 TODO: check with someone who knows for sure if that's correct.)
763 cltmadd RT, RA, RB, RC
766 TODO: add link to explanation for where `RS` comes from.
771 # read all inputs before writing to any outputs in case
772 # an input overlaps with an output register.
773 (RT) = clmul(a, (RB)) ^ c
777 ## `cldivrem` Carry-less Division and Remainder
779 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
780 for other instructions.
783 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
786 ## `cldiv` Carry-less Division
795 q, r = cldivrem(n, d, width=XLEN)
799 ## `clrem` Carry-less Remainder
808 q, r = cldivrem(n, d, width=XLEN)
812 # Instructions for Binary Galois Fields `GF(2^m)`
816 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
817 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
818 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
820 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
821 instruction is not provided since the `xor[i]` instruction can be used instead.
823 ## `GFBREDPOLY` SPR -- Reducing Polynomial
825 In order to save registers and to make operations orthogonal with standard
826 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
827 This also allows hardware to pre-compute useful parameters (such as the
828 degree, or look-up tables) based on the reducing polynomial, and store them
829 alongside the SPR in hidden registers, only recomputing them whenever the SPR
830 is written to, rather than having to recompute those values for every
833 Because Galois Fields require the reducing polynomial to be an irreducible
834 polynomial, that guarantees that any polynomial of `degree > 1` must have
835 the LSB set, since otherwise it would be divisible by the polynomial `x`,
836 making it reducible, making whatever we're working on no longer a Field.
837 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
840 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
843 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
845 unless this is an immediate op, `mtspr` is completely sufficient.
848 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
851 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
858 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
861 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
864 gfbmadd RT, RA, RB, RC
868 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
871 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
873 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
874 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
875 for a temp register. RS is written to as well as RT.
878 gfbtmadd RT, RA, RB, RC
881 TODO: add link to explanation for where `RS` comes from.
886 # read all inputs before writing to any outputs in case
887 # an input overlaps with an output register.
888 (RT) = gfbmadd(a, (RB), c)
889 # use gfbmadd again since it reduces the result
890 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
893 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
900 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
903 # Instructions for Prime Galois Fields `GF(p)`
905 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
907 ## `gfpadd` Prime Galois Field `GF(p)` Addition
914 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
917 the addition happens on infinite-precision integers
919 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
926 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
929 the subtraction happens on infinite-precision integers
931 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
938 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
941 the multiplication happens on infinite-precision integers
943 ## `gfpinv` Prime Galois Field `GF(p)` Invert
949 Some potential hardware implementations are found in:
950 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
953 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
956 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
959 gfpmadd RT, RA, RB, RC
963 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
966 the multiplication and addition happens on infinite-precision integers
968 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
971 gfpmsub RT, RA, RB, RC
975 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
978 the multiplication and subtraction happens on infinite-precision integers
980 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
983 gfpmsubr RT, RA, RB, RC
987 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
990 the multiplication and subtraction happens on infinite-precision integers
992 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
994 Used in combination with SV FFT REMAP to perform
995 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
996 to avoid the need for a temp register. RS is written
1000 gfpmaddsubr RT, RA, RB, RC
1003 TODO: add link to explanation for where `RS` comes from.
1009 # read all inputs before writing to any outputs in case
1010 # an input overlaps with an output register.
1011 (RT) = gfpmadd(factor1, factor2, term)
1012 (RS) = gfpmsubr(factor1, factor2, term)
1015 # Already in POWER ISA or subsumed
1017 Lists operations either included as part of
1018 other bitmanip operations, or are already in
1023 based on RV bitmanip, covered by ternlog bitops
1026 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1027 return (RA & RB) | (RC & ~RB);
1031 ## count leading/trailing zeros with mask
1037 do i = 0 to 63 if((RB)i=1) then do
1038 if((RS)i=1) then break end end count ← count + 1
1044 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1047 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1048 result = VSR[VRA+32].dword[i].bit[63-k]
1049 VSR[VRT+32].dword[i].bit[63-m] = result
1055 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1058 for (int i = 0, j = 0; i < XLEN; i++)
1059 if ((RB >> i) & 1) {
1061 r |= uint_xlen_t(1) << i;
1071 other way round: identical to RV bext: pextd, found in v3.1 p196
1074 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1077 for (int i = 0, j = 0; i < XLEN; i++)
1078 if ((RB >> i) & 1) {
1080 r |= uint_xlen_t(1) << j;
1089 found in v3.1 p106 so not to be added here
1099 if((RB)63-i==1) then do
1100 result63-ptr1 = (RS)63-i
1106 ## bit to byte permute
1108 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1109 these perform a transpose (bmatflip).
1110 TODO this looks VSX is there a scalar variant
1115 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1116 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1120 superceded by grevlut
1122 based on RV bitmanip, this is also known as a butterfly network. however
1123 where a butterfly network allows setting of every crossbar setting in
1124 every row and every column, generalised-reverse (grev) only allows
1125 a per-row decision: every entry in the same row must either switch or
1128 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1131 uint64_t grev64(uint64_t RA, uint64_t RB)
1134 int shamt = RB & 63;
1135 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1136 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1137 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1138 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1139 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1140 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1141 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1142 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1143 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1144 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1145 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1146 ((x & 0xFFFFFFFF00000000LL) >> 32);
1154 based on RV bitmanip, gorc is superceded by grevlut
1157 uint32_t gorc32(uint32_t RA, uint32_t RB)
1160 int shamt = RB & 31;
1161 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1162 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1163 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1164 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1165 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1168 uint64_t gorc64(uint64_t RA, uint64_t RB)
1171 int shamt = RB & 63;
1172 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1173 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1174 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1175 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1176 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1177 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1178 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1179 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1180 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1181 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1182 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1183 ((x & 0xFFFFFFFF00000000LL) >> 32);
1192 see [[bitmanip/appendix]]