openpower/sv/cr_ops.mdwn

   1 [[!tag standards]]
   2 # Condition Register SVP64 Operations
   3
   4 Links:
   5
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
   7 * [[svp64]]
   8 * [[sv/branches]]
   9 * [[openpower/isa/sprset]]
  10 * [[openpower/isa/condition]]
  11 * [[openpower/isa/comparefixed]]
  12
  13 Condition Register Fields are only 4 bits wide: this presents some
  14 interesting conceptual challenges for SVP64, particularly with respect to element
  15 width (which is clearly meaningless for a 4-bit
  16 collation of Conditions, EQ LT GE SO). Likewise, arithmetic saturation
  17 (an important part of Arithmetic SVP64)
  18 has no meaning. Additionally, extra modes are required that only make
  19 sense for Vectorised CR Operations. Consequently an alternative Mode Format is required.
  20
  21 This alternative mapping **only** applies to instructions that **only**
  22 reference a CR Field or CR bit as the sole exclusive result. This section
  23 **does not** apply to instructions which primarily produce arithmetic
  24 results that also, as an aside, produce a corresponding
  25 CR Field (such as when Rc=1).
  26 Instructions that involve Rc=1 are definitively arithmetic in nature,
  27 where the corresponding Condition Register Field can be considered to
  28 be a "co-result". Such CR Field "co-result" arithmeric operations
  29 are firmly out of scope for
  30 this section.
  31
  32 * Examples of v3.0B instructions to which this section does
  33   apply is
  34   - `mfcr` (3 bit operands) and
  35   - `crnor` and `cmpi` (5 bit operands).
  36 * Examples to which this section does **not** apply include
  37   `fadds.` and `subf.` which both produce arithmetic results
  38   (and a CR Field co-result).
  39
  40 The CR Mode Format still applies to `sv.cmpi` because despite
  41 taking a GPR as input, the output from the Base Scalar v3.0B `cmpi`
  42 instruction is purely to a Condition Register Field.
  43
  44 Other modes are still applicable and include:
  45
  46 * **Data-dependent fail-first**.
  47   useful to truncate VL based on
  48   analysis of a Condition Register result bit.
  49 * **Scalar and parallel reduction**.
  50   Reduction is useful
  51 for analysing a Vector of Condition Register Fields
  52 and reducing it to one
  53 single Condition Register Field.
  54 * **Predicate-result**.
  55   Equivalent
  56 to python "filter", in that only elements which pass a test
  57 will end up actually being modified. This is in effect the same
  58 as ANDing the Condition Test with the destination predicate
  59 mask (hence the name, "predicate-result").
  60
  61 Predicate-result is a particularly powerful strategic mode
  62 in that it is the interaction of a source predicate, destination predicate,
  63 input operands *and* the output result, all combining to influence
  64 what actually goes into the Condition Register File. Given that
  65 predicates may themselves be Condition Registers it can be seen that
  66 there could potentially be up to **six** CR Fields involved in
  67 the execution of Predicate-result Mode.
  68
  69 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  70
  71 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  72 | - | - | ----- | --- |---------|----------------- |
  73 |sz |SNZ| 00    |   0 |  dz  /  | normal mode                      |
  74 |sz |SNZ| 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  75 |sz |SNZ| 00    |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
  76 |sz |SNZ| 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  77 |sz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
  78 |sz |SNZ| 01/10 | inv |  dz /   | Ffirst 5-bit mode       |
  79 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  80 |sz |SNZ| 11    | inv | dz  /   |  5-bit pred-result z/nonz |
  81
  82 `VLI=0` when bits 19-20=0b01.
  83 `VLI=1` when bits 19-20=0b10.
  84
  85 Fields:
  86
  87 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
  88 * **SNZ** when sz=1 and SNZ=1 a value "1" is put in place of zeros when
  89   the predicate bit is clear.
  90 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
  91 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
  92 than the normal 0..VL-1
  93 * **SVM** sets "subvector" reduce mode
  94 * **VLi** VL inclusive: in fail-first mode, the truncation of
  95   VL *includes* the current element at the failure point rather
  96   than excludes it from the count.
  97
  98 # Data-dependent fail-first on CR operations
  99
 100 The principle of data-dependent fail-first is that if a Condition Test
 101 fails then VL (Vector Length) is truncated at that point. In the case
 102 of Arithmetic SVP64 Operations the Condition Register Field generated from
 103 Rc=1 is used as the basis for the truncation decision,
 104 however with CR-based operations that CR result is provided
 105 by the operation itself.
 106
 107 Data-dependent SVP64 Vectorised Operations involving the creation or
 108 modification of a CR can require an extra two bits, which are not available
 109 in the compact space of the SVP64 RM `MODE` Field. With the concept of element
 110 width overrides being meaningless for CR Fields it is possible to use the
 111 `ELWIDTH` field for alternative purposes.
 112
 113 Condition Register based operations such as `sv.mfcr` and `sv.crand` can thus
 114 be made more flexible.  However the rules that apply in this section
 115 also apply to future CR-based instructions.
 116
 117 There are two primary different types of CR operations:
 118
 119 * Those which have a 3-bit operand field (referring to a CR Field)
 120 * Those which have a 5-bit operand (referring to a bit within the
 121    whole 32-bit CR)
 122
 123 Examining these two types it is observed that the
 124 difference may be considered to be that the 5-bit variant
 125 *already* provides the
 126 prerequisite information about which CR Field bit (EQ, GE, LT, SO) is to
 127 be operated on by the instruction.
 128 Thus, logically, we may set the following rule:
 129
 130 * When a 5-bit CR Result field is used in an instruction, the
 131   5-bit variant of Data-Dependent Fail-First
 132   must be used. i.e. the bit of the CR field to be tested is
 133   the one that has just been modified (created) by the operation.
 134 * When a 3-bit CR Result field is used the 3-bit variant
 135   must be used, providing as it does the missing `CRbit` field
 136   in order to select which CR Field bit of the result shall
 137   be tested (EQ, LE, GE, SO)
 138
 139 The reason why the 3-bit CR variant needs the additional CR-bit
 140 field should be obvious from the fact that the 3-bit CR Field
 141 from the base Power ISA v3.0B operation clearly does not contain
 142 and is missing the two CR Field Selector bits. Thus, these two
 143 bits (to select EQ, LE, GE or SO) must be provided in another
 144 way.
 145
 146 Examples of the former type:
 147
 148 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
 149   to be tested against `inv` is the one selected by `BT`
 150 * mcrf. This has only 3-bit (BF, BFA). In order to select the
 151   bit to be tested, the alternative encoding must be used.
 152   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
 153   of BF to be tested is identified.
 154
 155 Just as with SVP64 [[sv/branches]] there is the option to truncate
 156 VL to include the element being tested (`VLi=1`) and to exclude it
 157 (`VLi=0`).
 158
 159 # Predicate-result Condition Register operations
 160
 161 These are again slightly different compared to SVP64 arithmetic
 162 pred-result (described in [[svp64/appendix]]). The reason is that,
 163 again, for arithmetic operations the production of a CR Field when
 164 Rc=1 is a *co-result* accompanying the main arithmetic result, whereas
 165 for CR-based operations the CR Field (referred to by a 3-bit
 166 v3.0B base operand from e.g. `mfcr`) or CR bit (referred to by a 5-bit operand from e.g. `crnor`)
 167 *is* itself the explicit and sole result of the operation.
 168
 169 Therefore, logically, Predicate-result needs to be adapted to
 170 test the actual result of the CR-based instruction (rather than
 171 test the co-resultant CR when Rc=1, as is done for Arithmetic SVP64).
 172
 173     for i in range(VL):
 174         # predication test, skip all masked out elements.
 175         # skips when sz=0
 176         if sz=0 and predicate_masked_out(i):
 177              continue
 178         if predicate_masked_out(i):
 179            if 5bit mode:
 180               # only one bit of CR to update
 181               result = SNZ
 182            else
 183               # four copies of SNZ
 184               result = SNZ || SNZ || SNZ || SNZ
 185         else
 186            # result is to go into CR. may be a 4-bit CR Field
 187            # (3-bit mode) or just a single bit (5-bit mode)
 188            result = op(...)
 189         if 5bit mode:
 190            # if this CR op has 5-bit CR result operands
 191            # the single bit result is what must be tested
 192            to_test = result
 193         else
 194            # if however this is a 3-bit CR *field* result
 195            # then the bit to be tested must be selected
 196            to_test = result[CRbit]
 197         # now test CR, similar to branch
 198         if to_test != inv:
 199             continue # test failed: cancel store
 200         # result optionally stored
 201         update_CR(result)