openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
  23 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
  24 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
  25
  26 # Code to convert
  27
  28 There are five projects:
  29
  30 * TestIssuer (the HDL)
  31 * ISACaller (the python-based simulator)
  32 * power-gem5 (a cycle accurate simulator)
  33 * Microwatt (VHDL)
  34 * gcc and binutils
  35
  36 Each of these needs to have SV augmentation, and the best way to
  37 do it is if they are all done at the same time, implementing the same
  38 incremental feature.
  39
  40 # Critical tasks
  41
  42 These are prerequisite tasks:
  43
  44 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  45   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  46   just use pygdbmi
  47   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  48 * c++, c and python macros for generating [[sv/svp64]] assembler
  49   (svp64 prefixes)
  50   - python svp64 underway, minimalist sufficient for FU unit tests
  51 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  52 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  53   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  54   - INT and CR EXTRA svp64 fields completed.
  55 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  56
  57 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  58
  59 * Lauri:
  60 * Jacob: C/C++ header for using SV through inline assembly
  61 * Cesar: TestIssuer FSM
  62 * Alain: power-gem5
  63 * Cole:
  64 * Luke: ISACaller, python-assembler-generator-class
  65 * Tobias:
  66 * Alexandre: binutils-svp64-assembler and gcc
  67 * Paul: microwatt
  68
  69 # Adding SV
  70
  71 order: listed in [[sv/overview]]
  72
  73 ## svp64 decoder
  74
  75 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  76
  77 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  78 * power-gem5: TODO
  79 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  80 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  81 * python-based assembler-translator: 40% done (lkcl)
  82 * c++ macros: underway (jacob)
  83
  84 Note when decoding the RM into bits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  85
  86 **IMPORTANT**! when spotting RA=0 in some instructions it is critical to note that the *full **seven** bits* are used (those from EXTRA2/3 included) because RA is no longer only five bits.
  87
  88 Links:
  89
  90 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  91 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  92 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  93
  94 ## SVSTATE SPR needed
  95
  96 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  97
  98 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  99
 100     num name    priv  width
 101     704,SVSTATE,no,no,32
 102     720,SVSRR0,yes,yes,32
 103
 104 Progress:
 105
 106 * ISACaller: done
 107 * power-gem5: TODO
 108 * TestIssuer: TODO
 109 * Microwatt: TODO
 110
 111 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 112
 113 ## Adding SVSTATE "set/get" support for hw/sw debugging
 114
 115 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 116
 117 * LibreSOC DMI/JTAG: TODO
 118 * Microwatt DMI: TODO
 119 * power-gem5 remote gdb: TODO
 120 * TestIssuer: DONE (read-only at least) <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=4d5482810c980ff927ccec62968a40a490ea86eb>
 121
 122 Links:
 123
 124 * <https://bugs.libre-soc.org/show_bug.cgi?id=609>
 125
 126 ## sv.setvl
 127
 128 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 129
 130 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 131 * ISACaller: TODO
 132 * power-gem5: TODO
 133 * TestIssuer: TODO
 134 * Microwatt: TODO
 135
 136 Links:
 137
 138 ## SVSRR0 for exceptions
 139
 140 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 141
 142 * ISACaller: TODO
 143 * power-gem5: TODO
 144 * TestIssuer: TODO
 145 * Microwatt: TODO
 146
 147 ## Illegal instruction exceptions
 148
 149 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 150
 151 * ISACaller: TODO
 152 * power-gem5: TODO
 153 * TestIssuer: TODO
 154 * Microwatt: TODO
 155
 156 ## VL for-loop
 157
 158 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 159
 160 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 161
 162 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 163
 164 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 165
 166 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 167 * power-gem5: TODO
 168 * TestIssuer:
 169   - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 170   - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 171 * Microwatt: TODO
 172
 173 Remember the following register files need to have for-loops, plus
 174 unit tests:
 175
 176 * GPR
 177 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 178 * Condition Registers.  see note below
 179 * FPR (if present)
 180
 181 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 182
 183 ## Increasing register file sizes
 184
 185 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 186
 187 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 188
 189 ## Single and Twin Predication
 190
 191 both CR and INT predication is needed, as well as zeroing in both
 192
 193 * INT-based single: TODO
 194 * CR-based single:  TODO
 195 * INT-based twin:   TODO
 196 * CR-based twin:    TODO
 197 * Zeroing single:   TODO
 198 * Zeroing twin:     TODO
 199
 200 Progress:
 201
 202 * TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617>
 203 * ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=618>
 204 * power-gem5: TODO
 205 * Microwatt: TODO
 206
 207 ## Element width overrides
 208
 209 TODO