openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22
  23 # Code to convert
  24
  25 There are five projects:
  26
  27 * TestIssuer (the HDL)
  28 * ISACaller (the python-based simulator)
  29 * power-gem5 (a cycle accurate simulator)
  30 * Microwatt (VHDL)
  31 * gcc and binutils
  32
  33 Each of these needs to have SV augmentation, and the best way to
  34 do it is if they are all done at the same time, implementing the same
  35 incremental feature.
  36
  37 # Critical tasks
  38
  39 These are prerequisite tasks:
  40
  41 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  42   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  43   just use pygdbmi
  44   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  45 * c++, c and python macros for generating [[sv/svp64]] assembler
  46   (svp64 prefixes)
  47   - python svp64 underway, minimalist sufficient for FU unit tests
  48 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  49 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  50   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  51   - INT and CR EXTRA svp64 fields completed.
  52 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  53
  54 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  55
  56 * Lauri:
  57 * Jacob: C/C++ header for using SV through inline assembly
  58 * Cesar: TestIssuer FSM
  59 * Alain: power-gem5
  60 * Cole:
  61 * Luke: ISACaller, python-assembler-generator-class
  62 * Tobias:
  63 * Alexandre: binutils-svp64-assembler and gcc
  64 * Paul: microwatt
  65
  66 # Adding SV
  67
  68 order: listed in [[sv/overview]]
  69
  70 ## svp64 decoder
  71
  72 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  73
  74 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  75 * power-gem5: TODO
  76 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  77 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  78 * python-based assembler-translator: 40% done (lkcl)
  79 * c++ macros: underway (jacob)
  80
  81 Note when decoding the RM intobits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  82
  83 Links:
  84
  85 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  86 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  87 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  88
  89 ## SVSTATE SPR needed
  90
  91 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  92
  93 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  94
  95     num name    priv  width
  96     704,SVSTATE,no,no,32
  97     720,SVSRR0,yes,yes,32
  98
  99 Progress:
 100
 101 * ISACaller: done
 102 * power-gem5: TODO
 103 * TestIssuer: TODO
 104 * Microwatt: TODO
 105
 106 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 107
 108 ## Adding SVSTATE "set/get" support for hw/sw debugging
 109
 110 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 111
 112 * LibreSOC DMI/JTAG: TODO
 113 * Microwatt DMI: TODO
 114 * power-gem5 remote gdb: TODO
 115 * TestIssuer: TODO
 116
 117 Links:
 118
 119 * <https://bugs.libre-soc.org/show_bug.cgi?id=609>
 120
 121 ## sv.setvl
 122
 123 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 124
 125 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 126 * ISACaller: TODO
 127 * power-gem5: TODO
 128 * TestIssuer: TODO
 129 * Microwatt: TODO
 130
 131 Links:
 132
 133 ## SVSRR0 for exceptions
 134
 135 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 136
 137 * ISACaller: TODO
 138 * power-gem5: TODO
 139 * TestIssuer: TODO
 140 * Microwatt: TODO
 141
 142 ## Illegal instruction exceptions
 143
 144 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 145
 146 * ISACaller: TODO
 147 * power-gem5: TODO
 148 * TestIssuer: TODO
 149 * Microwatt: TODO
 150
 151 ## VL for-loop
 152
 153 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 154
 155 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 156
 157 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 158
 159 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 160
 161 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 162 * power-gem5: TODO
 163 * TestIssuer:
 164   - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 165   - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 166 * Microwatt: TODO
 167
 168 Remember the following register files need to have for-loops, plus
 169 unit tests:
 170
 171 * GPR
 172 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 173 * Condition Registers.  see note below
 174 * FPR (if present)
 175
 176 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 177
 178 ## Increasing register file sizes
 179
 180 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 181
 182 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 183
 184 ## Single Predication
 185
 186 TODO
 187
 188 ## Element width overrides
 189
 190 TODO