openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22
  23 # Code to convert
  24
  25 There are four projects:
  26
  27 * TestIssuer (the HDL)
  28 * ISACaller (the python-based simulator)
  29 * power-gem5 (a cycle accurate simulator)
  30 * Microwatt (VHDL)
  31
  32 Each of these needs to have SV augmentation, and the best way to
  33 do it is if they are all done at the same time, implementing the same
  34 incremental feature.
  35
  36 # Critical tasks
  37
  38 These are prerequisite tasks:
  39
  40 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  41   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  42   just use pygdbmi
  43   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  44 * c++, c and python macros for generating [[sv/svp64]] assembler
  45   (svp64 prefixes)
  46   - python svp64 underway, minimalist sufficient for FU unit tests
  47 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  48 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  49   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  50   - INT and CR EXTRA svp64 fields completed.
  51 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  52
  53 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  54
  55 * Lauri:
  56 * Jacob: C/C++ header for using SV through inline assembly
  57 * Cesar: TestIssuer FSM
  58 * Alain: power-gem5
  59 * Cole:
  60 * Luke: ISACaller, python-assembler-generator-class
  61 * Tobias:
  62 * Alexandre: binutils-svp64-assembler
  63 * Paul: microwatt
  64
  65 # Adding SV
  66
  67 order: listed in [[sv/overview]]
  68
  69 ## svp64 decoder
  70
  71 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  72
  73 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  74 * power-gem5: TODO
  75 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  76 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  77 * python-based assembler-translator: 40% done (lkcl)
  78 * c++ macros: underway (jacob)
  79
  80 Note when decoding the RM intobits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  81
  82 Links:
  83
  84 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  85 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  86 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  87
  88 ## SVSTATE SPR needed
  89
  90 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  91
  92 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  93
  94     num name    priv  width
  95     704,SVSTATE,no,no,32
  96     720,SVSRR0,yes,yes,32
  97
  98 Progress:
  99
 100 * ISACaller: done
 101 * power-gem5: TODO
 102 * TestIssuer: TODO
 103 * Microwatt: TODO
 104
 105 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 106
 107 ## Adding SVSTATE "set/get" support for hw/sw debugging
 108
 109 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 110
 111 * LibreSOC DMI/JTAG: TODO
 112 * Microwatt DMI: TODO
 113 * power-gem5 remote gdb: TODO
 114 * TestIssuer: TODO
 115
 116 ## sv.setvl
 117
 118 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 119
 120 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 121 * ISACaller: TODO
 122 * power-gem5: TODO
 123 * TestIssuer: TODO
 124 * Microwatt: TODO
 125
 126 ## SVSRR0 for exceptions
 127
 128 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 129
 130 * ISACaller: TODO
 131 * power-gem5: TODO
 132 * TestIssuer: TODO
 133 * Microwatt: TODO
 134
 135 ## Illegal instruction exceptions
 136
 137 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 138
 139 * ISACaller: TODO
 140 * power-gem5: TODO
 141 * TestIssuer: TODO
 142 * Microwatt: TODO
 143
 144 ## VL for-loop
 145
 146 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 147
 148 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 149
 150 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 151
 152 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 153
 154 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 155 * power-gem5: TODO
 156 * TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 157 * Microwatt: TODO
 158
 159 Remember the following register files need to have for-loops, plus
 160 unit tests:
 161
 162 * GPR
 163 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 164 * Condition Registers.  see note below
 165 * FPR (if present)
 166
 167 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 168
 169 ## Increasing register file sizes
 170
 171 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 172
 173 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 174
 175 ## Single Predication
 176
 177 TODO
 178
 179 ## Element width overrides
 180
 181 TODO