openpower/sv/po9_encoding.mdwn

   1 # Definitions
   2
   3 **Proposal: Add the following Definition to Section 1.3.1 of Book I**
   4
   5 **Definition of Simple-V:**
   6
   7 In its simpest form, the Simple-V Loop/Vector concept is a Prefixing
   8 system (sililar to the 8086 `REP` instruction) that both augments its
   9 following Defined Word Suffix, and also may repeat that instruction
  10 with optional sequential register offsets from those given in the
  11 Suffix. Register numbers may also be extended (larger register files).
  12 More advanced features add predication, element-width overrides, and
  13 Vertical-First Mode.
  14
  15 **Definition of SVP64 Prefixing:**
  16
  17 SVP64 is a well-defined implementation of the Simple-V Loop/Vector concept,
  18 in a 32-bit Prefix format, that exploits the following instruction
  19 (the Defined Word) using it as a "template".  It requires 24 bits,
  20 some of which are common to all Suffixes, and some Mode bits are specific
  21 to the Defined Word class: Load/Store-Immediate, Load/Store-Indexed,
  22 Arithmetic/Logical, Condition Register operations, and Branch-Conditional.
  23 Anything not falling into those five categories is termed "UnVectoriseable".
  24
  25 **Definition of Vertical-First:**
  26
  27 Normal Cray-style Vectorisation, designated Horizontal-First, performs
  28 element-level operations (often in parallel) before moving in the usual
  29 fashion to the next instruction. Vertical-First on the other hand executes
  30 *one element operation only* then moves on to the next instruction,
  31 whereupon if that is also an SVP64-Prefixed instruction the exact same
  32 element offset is used.  Element offsets are then explicitly advanced
  33 by calling a special instruction, `svstep`. The term "Vertical-First"
  34 stems from visually listing program instructions vertically and register
  35 files horizontally.
  36
  37 **Definition of SVP64Single Prefixing:**
  38
  39 A 32-bit Prefix in front of a Defined Word that extends register
  40 numbers (allows larger register files), adds single-bit predication,
  41 element-width overrides, and optionally adds Saturation to Arithmetic
  42 instructions that normally would not have it.  *SVP64 is in Draft only*
  43 and is yet to be defined.
  44
  45 **Definition of "UnVectoriseable":**
  46
  47 Any operation that inherently makes no sense if repeated (through SVP64
  48 Prefixing) is termed "UnVectoriseable" or "UnVectorised".  Examples
  49 include `sc` or `sync` which have no registers. `mtmsr` is also classed
  50 as UnVectoriseable because there is only one `MSR`.
  51
  52 UnVectorised instructions are required to be detected as such if Prefixed
  53 (either SVP64 or SVP64Single) and an Illegal Instruction Trap raised.
  54
  55 *Architectural Note: Given that a "pre-classification" Decode Phase
  56 is required (identifying whether the Suffix - Defined Word - is
  57 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding
  58 "UnVectorised" to this phase is not unreasonable.*
  59
  60 # New 64-bit Instruction Encoding spaces
  61
  62 **Proposal: Add new Section 1.6.5 to Book I**
  63
  64 The following seven new areas are defined within Primary Opcode 9 (EXT009)
  65 as a new 64-bit encoding space, alongside Primary Opcode 1
  66 (EXT1xx).
  67
  68 | 0-5 | 6 | 7 | 8-31  | 32| Description                        |
  69 |-----|---|---|-------|---|------------------------------------|
  70 | PO  | 0 | x | xxxx  | 0 | `RESERVED2` (57-bit) |
  71 | PO  | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
  72 | PO  | 0 | 0 | 0000  | 1 | Scalar EXT232-263               |
  73 | PO  | 0 | 1 | nnnn  | 1 | SVP64:EXT232-263     |
  74 | PO  | 1 | 0 | 0000  | x | `RESERVED1` (32-bit) |
  75 | PO  | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
  76 | PO  | 1 | 1 | nnnn  | n | SVP64:EXT000-063       |
  77
  78 Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
  79 it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
  80 for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
  81 prohibition allows SVP64Single to share its Encoding space with Scalar
  82 Ext232-263 and Scalar EXT300-363.
  83
  84 Also that RESERVED1 and 2 are candidates for future Major opcode
  85 areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas
  86 they may equally be allocated entirely differently.
  87
  88 *Architectural Resource Allocation Note: **under no circumstances** must
  89 different Defined Words be allocated within any `EXT{z}` prefixed or
  90 unprefixed space for a given value of `z` of 0, 2 or 3. Even if UnVectoriseable
  91 an instruction Defined Word space must have the exact same Instruction
  92 and exact same Instruction Encoding in all spaces being RESERVED (Illegal
  93 Instruction Trap if UnVectoriseable) or not be allocated at all.
  94 This is required as an inviolate hard rule governing Primary Opcode 9
  95 that may not be revoked under any circumstances. A useful way to think
  96 of this is that the Prefix Encoding is, like the 8086 REP instruction,
  97 an independent 32-bit Defined Word. The only semi-exceptions are
  98 the Post-Increment Mode of LD/ST-Update and Vectorised Branch-Conditional.*
  99
 100 Encoding spaces and their potential are illustrated:
 101
 102 | Encoding |Available bits|Scalar|Vectoriseable | SVP64Single  |PO1-Prefixable |
 103 |----------|--------------|------|--------------|--------------|---------------|
 104 |EXT000-063| 32           | yes  | yes          |yes           |yes            |
 105 |EXT100-163| 64           | yes  | no           |no            |not twice      |
 106 |RESERVED2 | 57           | N/A  |not applicable|not applicable|not applicable |
 107 |EXT232-263| 32           | yes  | yes          |yes           |no             |
 108 |RESERVED1 | 32           | N/A  | no           |no            |no             |
 109
 110 Notes:
 111
 112 * Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
 113   thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit
 114   on top of an SVP64 prefix which is 32-bit on top of a Defined Word
 115   and the complexity at the Decoder becomes too great for High
 116   Performance Multi-Issue systems.
 117 * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being
 118   double-PO1-prefixed (not twice prefixed)
 119 * RESERVED2 presently remains unallocated as of yet and therefore its
 120   potential is not yet defined (Not Applicable).
 121 * RESERVED1 is also unallocated at present, but it is known in advance
 122   that the area is UnVectoriseable and also cannot be Prefixed with
 123   SVP64Single.
 124 * Considerable care is needed both on Architectural Resource Allocation
 125   as well as instruction design itself.  Once an instruction is allocated
 126   in an UnVectoriseable area it can never be Vectorised without providing
 127   an entirely new Encoding.
 128
 129 [[!tag standards]]
 130
 131 --------
 132
 133 \newpage{}
 134