openpower/sv/rfc/ls004.mdwn

   1 # RFC ls004  Shift-And-Add
   2
   3 **URLs**:
   4
   5 * <https://libre-soc.org/openpower/sv/biginteger/analysis/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls004/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=960>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/91>
   9 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
  10
  11 **Severity**: Major
  12
  13 **Status**: New
  14
  15 **Date**: 31 Oct 2022
  16
  17 **Target**: v3.2B
  18
  19 **Source**: v3.0B
  20
  21 **Books and Section affected**:
  22
  23 ```
  24     Book I Fixed-Point Shift Instructions 3.3.14.2
  25     Appendix E Power ISA sorted by opcode
  26     Appendix F Power ISA sorted by version
  27     Appendix G Power ISA sorted by Compliancy Subset
  28     Appendix H Power ISA sorted by mnemonic
  29 ```
  30
  31 **Summary**
  32
  33 ```
  34     Instructions added
  35     shadd - Shift and Add
  36     shadduw - Shift and Add Unsigned Word
  37 ```
  38
  39 **Submitter**: Luke Leighton (Libre-SOC)
  40
  41 **Requester**: Libre-SOC
  42
  43 **Impact on processor**:
  44
  45 ```
  46     Addition of two new GPR-based instructions
  47 ```
  48
  49 **Impact on software**:
  50
  51 ```
  52     Requires support for new instructions in assembler, debuggers,
  53     and related tools.
  54 ```
  55
  56 **Keywords**:
  57
  58 ```
  59     GPR, Big-manip, Shift, Arithmetic
  60 ```
  61
  62 **Motivation**
  63
  64 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
  65 Adding more LD/ST is too complex, a compromise is to add shift-and-add.
  66 Replaces a pair of explicit instructions in hot-loops.
  67
  68 **Notes and Observations**:
  69
  70 1. `shadd` and `shadduw` operate on unsigned integers.
  71 2. `shadduw` is intended for performing address offsets,
  72    as the second operand is constrained to lower 32-bits
  73    and sign-extended.
  74 3. Both are 2-in 1-out instructions.
  75
  76 **Changes**
  77
  78 Add the following entries to:
  79
  80 * the Appendices of Book I
  81 * Instructions of Book I added to Section 3.3.14.2
  82
  83 ----------------
  84
  85 \newpage{}
  86
  87 # Shift-and-Add
  88
  89 `shadd RT, RA, RB`
  90
  91 |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
  92 |-------|------|-------|-------|-------|-------|----|----------|
  93 |  PO   | RT   |  RA   |  RB   |  sm   |  XO   | Rc | Z23-Form |
  94
  95 Pseudocode:
  96
  97     shift <- sm + 1                                 # Shift is between 1-4
  98     sum[0:63] <- ((RB) << shift) + (RA) # Shift RB, add RA
  99     RT <- sum                                       # Result stored in RT
 100
 101 When `sm` is zero, the contents of register RB are multiplied by 2,
 102 added to the contents of register RA, and the result stored in RT.
 103
 104 `sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
 105
 106 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 107
 108 **NEED EXAMPLES (not sure how to embedd sm)!!!**
 109 Examples:
 110
 111 ```
 112 # adds r1 to (r2*8)
 113 shadd r4, r1, r2, 3
 114 ```
 115
 116 # Shift-and-Add Unsigned Word
 117
 118 `shadd RT, RA, RB`
 119
 120 |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
 121 |-------|------|-------|-------|-------|-------|----|----------|
 122 |  PO   | RT   |  RA   |  RB   |  sm   |  XO   | Rc | Z23-Form |
 123
 124 Pseudocode:
 125
 126     shift <- sm + 1                                     # Shift is between 1-4
 127     n <- (RB)[32:63]                            # Only use lower 32-bits of RB
 128     sum[0:63] <- (n << shift) + (RA)    # Shift n, add RA
 129     RT <- sum                                       # Result stored in RT
 130
 131 When `sm` is zero, the lower word contents of register RB are multiplied by 2,
 132 added to the contents of register RA, and the result stored in RT.
 133
 134 `sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
 135
 136 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 137
 138 *Programmer's Note:
 139 The advantage of this instruction is doing address offsets. RA is the base 64-bit
 140 address. RB is the offset into data structure limited to 32-bit.
 141
 142 Examples:
 143
 144 ```
 145 #
 146 shadduw r4, r1, r2
 147 ```
 148
 149
 150 [[!tag opf_rfc]]
 151
 152 # Appendices
 153
 154     Appendix E Power ISA sorted by opcode
 155     Appendix F Power ISA sorted by version
 156     Appendix G Power ISA sorted by Compliancy Subset
 157     Appendix H Power ISA sorted by mnemonic
 158
 159 | Form | Book | Page | Version | mnemonic | Description |
 160 |------|------|------|---------|----------|-------------|
 161 | Z23  | I    | #    | 3.0B    | shadd    | Shift-and-Add |
 162 | Z23  | I    | #    | 3.0B    | shadduw  | Shift-and-Add Unsigned Word |
 163