1 # RFC ls004 Shift-And-Add
5 * <https://libre-soc.org/openpower/sv/biginteger/analysis/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls004/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=960>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/91>
9 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
21 **Books and Section affected**:
24 Book I Fixed-Point Shift Instructions 3.3.14.2
25 Appendix E Power ISA sorted by opcode
26 Appendix F Power ISA sorted by version
27 Appendix G Power ISA sorted by Compliancy Subset
28 Appendix H Power ISA sorted by mnemonic
36 shadduw - Shift and Add Unsigned Word
39 **Submitter**: Luke Leighton (Libre-SOC)
41 **Requester**: Libre-SOC
43 **Impact on processor**:
46 Addition of two new GPR-based instructions
49 **Impact on software**:
52 Requires support for new instructions in assembler, debuggers,
59 GPR, Big-manip, Shift, Arithmetic
64 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
65 Adding more LD/ST is too complex, a compromise is to add shift-and-add.
66 Replaces a pair of explicit instructions in hot-loops.
68 **Notes and Observations**:
70 1. `shadd` and `shadduw` operate on unsigned integers.
71 2. `shadduw` masks the upper 32-bits of the operand to-be-shifted.
72 3. These are both 2-in 1-out instructions.
76 Add the following entries to:
78 * the Appendices of Book I
79 * Instructions of Book I added to Section 3.3.14.2
89 | 0-5 | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form |
90 |-------|------|-------|-------|-------|-------|----|----------|
91 | PO | RT | RA | RB | sm | XO | Rc | Z23-Form |
95 shift <- sm + 1 # Shift is between 1-4
96 sum[0:63] <- ((RB) << shift) + (RA) # Shift RB, add RA
97 RT <- sum # Result stored in RT
99 When `sm` is zero, the contents of register RB are multiplied by 2,
100 added to the contents of register RA, and the result stored in RT.
102 `sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
104 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
106 **NEED EXAMPLES (not sure how to embedd sm)!!!**
114 # Shift-and-Add Unsigned Word
118 | 0-5 | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form |
119 |-------|------|-------|-------|-------|-------|----|----------|
120 | PO | RT | RA | RB | sm | XO | Rc | Z23-Form |
124 shift <- sm + 1 # Shift is between 1-4
125 n <- (RB)[XLEN/2:XLEN-1] # Limit RB to upper word (32-bits)
126 sum[0:63] <- (n << shift) + (RA) # Shift n, add RA
127 RT <- sum # Result stored in RT
129 When `sm` is zero, the upper word contents of register RB are multiplied by 2,
130 added to the contents of register RA, and the result stored in RT.
132 `sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
134 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
148 Appendix E Power ISA sorted by opcode
149 Appendix F Power ISA sorted by version
150 Appendix G Power ISA sorted by Compliancy Subset
151 Appendix H Power ISA sorted by mnemonic
153 | Form | Book | Page | Version | mnemonic | Description |
154 |------|------|------|---------|----------|-------------|
155 | Z23 | I | # | 3.0B | shadd | Shift-and-Add |
156 | Z23 | I | # | 3.0B | shadduw | Shift-and-Add Unsigned Word |