openpower/sv/rfc/ls005.mdwn

   1 # OPF ISA WG External RFC ls005 v1: XLEN
   2
   3 * RFC Author: Luke Kenneth Casson Leighton.
   4 * RFC Contributors/Ideas: Jacob Lifshay, Toshaan Bharvani
   5 * Funded by NLnet under the NGI Zero Entrust EU Horizon Europe Grant 101069594
   6
   7 **URLs**:
   8
   9 * <https://libre-soc.org/openpower/sv/rfc/ls005/>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=663>
  11 * <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD>
  12 * <https://git.openpower.foundation/isa/PowerISA/issues/104>
  13
  14 **Severity**: Major
  15
  16 **Status**: New
  17
  18 **Date**: 22 Dec 2022
  19
  20 **Target**: v3.2B
  21
  22 **Source**: v3.0B
  23
  24 **Books and Section affected**:
  25
  26 ```
  27     Everything (in a consistent, regular and systematic fashion)
  28 ```
  29
  30 **Summary**
  31
  32 ```
  33     Exactly as is already done in RISC-V, convert the entire use of 64-bit hard-coding to "XLEN".
  34     Exactly as is in RISC-V, options then include PowerISA-32, PowerISA-64 and PowerISA-128.
  35     Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is also floated, for Embedded,
  36     AI, Edge, Processing-in-Memory, Distributed Computing and other purposes.
  37 ```
  38
  39 **Submitter**: Luke Leighton (Libre-SOC)
  40
  41 **Requester**: Libre-SOC
  42
  43 **Impact on processor**:
  44
  45 ```
  46     Entirely new processors, entirely new markets.
  47 ```
  48
  49 **Impact on software**:
  50
  51 ```
  52     Massive but regular, consistent, and systematic.
  53 ```
  54
  55 **Keywords**:
  56
  57 ```
  58     XLEN
  59 ```
  60
  61 **Motivation**
  62
  63 The Power ISA is far too massive, making it wholly unsuited for Embedded
  64 markets and adversely impacting its reach and potential.  The RISC paradigm
  65 it is based on has gone too far into PackedSIMD (128-bit).  Fixing this is
  66 relatively and conceptually straightforward: allow 32-bit and even 16-bit
  67 and 8-bit implementations, and use the opportunity to allow future Scalar
  68 128-bit implementations in the exact same strategic way that RISC-V has RV128.
  69
  70 Register files are redefined to XLEN width but are permitted to "group"
  71 registers together to create 16-bit, 32-bit and 64-bit addresses.
  72 In this way, the limitations of what would otherwise restrict the usefulness
  73 of a severely-targetted application-specific processor may be overcome in
  74 order to make it still possible to (at reduced performance) still run
  75 general-purpose applications.
  76 AI application-specific processing or other Processing-In-Memory or other
  77 specialist design therefore may for example focus a balance
  78 of raw computing power heavily onto 8-bit or 16-bit computation, but still
  79 gain the benefit of the Power ISA and everything it brings.  Contrast
  80 this with the more "normal" approach of creating heavily-focussed
  81 specialist "AI" Engines incapable of Turing-completeness and the benefits
  82 are clear.
  83
  84 Note: SVP64 **requires** this change as a 100% critical dependency.
  85 SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
  86 64-bit), read from, processed, and returned to, the standard **Scalar**
  87 Register Files, with byte-level write-enable lines.
  88
  89 **Changes**
  90
  91 For all pseudocode right across the board in all Scalar operations, replace
  92 hard-coded "64" with "XLEN".  **This work is already underway as sponsored
  93 by NLnet in the Libre-SOC Power ISA Pseudocode**.  The default is obviously
  94 recommended to be "XLEN=64" in order to create zero disruption.
  95
  96 Definitions of the Register File(s) for GPR and FPR are then changed to be
  97 "XLEN" wide.  However, for Embedded purposes (XLEN=32/16/8), an SPR controls
  98 whether (and how many) sequentially-grouped registers are taken together to
  99 create 16-bit, 32-bit and 64-bit addresses (depending on application need).
 100 GPR is obvious, FPR is quirky.  SVP64 redefines FP ops (those not ending in "s")
 101 to be "full width" and all ops ending in "s" to be "half of
 102 the FP width".
 103
 104 * XLEN=64 keeps FPR "full width" exactly as presently defined, and
 105   "half width" exactly as presently defined.
 106 * XLEN=32 overrides FPR "full width" operations to
 107   full FP32, and "half width" to be "FP16 stored in an FP32"
 108 * XLEN=16 redefines FPR "full width" operations to full BFP16 and leaves
 109   "half width" UNDEFINED (there is no FP8).
 110 * XLEN=8 redefines FPR "full width" operations to BF16 and leaves
 111   "half width" UNDEFINED (there is no BF8).
 112
 113 ----------------
 114
 115 \newpage{}
 116