openpower/sv/rfc/ls005.mdwn

   1 # OPF ISA WG External RFC ls005 v1: XLEN
   2
   3 * RFC Author: Luke Kenneth Casson Leighton.
   4 * RFC Contributors/Ideas: Jacob Lifshay, Toshaan Bharvani
   5 * Funded by NLnet under the NGI Zero Entrust EU Horizon Europe Grant 101069594
   6
   7 **URLs**:
   8
   9 * <https://libre-soc.org/openpower/sv/rfc/ls005/>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=663>
  11 * <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD>
  12 * <https://git.openpower.foundation/isa/PowerISA/issues/104>
  13
  14 **Severity**: Major
  15
  16 **Status**: New
  17
  18 **Date**: 22 Dec 2022
  19
  20 **Target**: v3.2B
  21
  22 **Source**: v3.0B
  23
  24 **Books and Section affected**:
  25
  26 ```
  27     Everything (in a consistent, regular and systematic fashion)
  28 ```
  29
  30 **Summary**
  31
  32 ```
  33     Exactly as is already done in RISC-V, convert the entire
  34     use of 64-bit hard-coding to "XLEN".  Exactly as is in RISC-V,
  35     options then include PowerISA-32, PowerISA-64 and PowerISA-128.
  36     Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is
  37     also floated, for Embedded, AI, Edge, Processing-in-Memory,
  38     Distributed Computing and other purposes.
  39 ```
  40
  41 **Submitter**: Luke Leighton (Libre-SOC)
  42
  43 **Requester**: Libre-SOC
  44
  45 **Impact on processor**:
  46
  47 ```
  48     Entirely new processors, entirely new markets.
  49 ```
  50
  51 **Impact on software**:
  52
  53 ```
  54     Massive but regular, consistent, and systematic.
  55 ```
  56
  57 **Keywords**:
  58
  59 ```
  60     XLEN
  61 ```
  62
  63 **Motivation**
  64
  65 The Power ISA is far too massive, making it wholly unsuited for Embedded
  66 markets and adversely impacting its reach and potential.  The RISC paradigm
  67 it is based on has gone too far into PackedSIMD (128-bit).  Fixing this is
  68 relatively and conceptually straightforward: allow 32-bit and even 16-bit
  69 and 8-bit implementations, and use the opportunity to allow future Scalar
  70 128-bit implementations in the exact same strategic way that RISC-V has RV128.
  71
  72 Register files are redefined to XLEN width but are permitted to "group"
  73 registers together to create 16-bit, 32-bit and 64-bit addresses.
  74 In this way, the limitations of what would otherwise restrict the usefulness
  75 of a severely-targetted application-specific processor may be overcome in
  76 order to make it still possible to (at reduced performance) still run
  77 general-purpose applications.
  78 AI application-specific processing or other Processing-In-Memory or other
  79 specialist design therefore may for example focus a balance
  80 of raw computing power heavily onto 8-bit or 16-bit computation, but still
  81 gain the benefit of the Power ISA and everything it brings.  Contrast
  82 this with the more "normal" approach of creating heavily-focussed
  83 specialist "AI" Engines incapable of Turing-completeness and the benefits
  84 are clear.
  85
  86 Note: SVP64 **requires** this change as a 100% critical dependency.
  87 SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
  88 64-bit), read from, processed, and returned to, the standard **Scalar**
  89 Register Files, with byte-level write-enable lines.
  90
  91 **Changes**
  92
  93 For all pseudocode right across the board in all Scalar operations, replace
  94 hard-coded "64" with "XLEN".  **This work is already underway as sponsored
  95 by NLnet in the Libre-SOC Power ISA Pseudocode**.  The default is obviously
  96 recommended to be "XLEN=64" in order to create zero disruption.
  97
  98 Definitions of the Register File(s) for GPR and FPR are then changed to be
  99 "XLEN" wide.  However, for Embedded purposes (XLEN=32/16/8), an SPR controls
 100 whether (and how many) sequentially-grouped registers are taken together to
 101 create 16-bit, 32-bit and 64-bit addresses (depending on application need).
 102 GPR is obvious, FPR is quirky.  SVP64 redefines FP ops (those not ending in "s")
 103 to be "full width" and all ops ending in "s" to be "half of
 104 the FP width".
 105
 106 * XLEN=64 keeps FPR "full width" exactly as presently defined, and
 107   "half width" exactly as presently defined.
 108 * XLEN=32 overrides FPR "full width" operations to
 109   full FP32, and "half width" to be "FP16 stored in an FP32"
 110 * XLEN=16 redefines FPR "full width" operations to full BFP16 and leaves
 111   "half width" UNDEFINED (there is no FP8).
 112 * XLEN=8 redefines FPR "full width" operations to BF16 and leaves
 113   "half width" UNDEFINED (there is no BF8).
 114
 115 ----------------
 116
 117 \newpage{}
 118