openpower/sv/rfc/ls008.mdwn

   1 # RFC ls008 SVP64 Management instructions
   2
   3 [[!tag opf_rfc]]
   4
   5 # RFC ls002 v2 Floating-Point Load-Immediate
   6
   7 **URLs**:
   8
   9 * <https://libre-soc.org/openpower/sv/int_fp_mv/#fmvis>
  10 * <https://libre-soc.org/openpower/sv/rfc/ls002/>
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=944>
  12 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
  13
  14 **Severity**: Major
  15
  16 **Status**: New
  17
  18 **Date**: 24 Mar 2023
  19
  20 **Target**: v3.2B
  21
  22 **Source**: v3.0B
  23
  24 **Books and Section affected**:
  25
  26 ```
  27     Book I Scalar Floating-Point 4.6.2.1
  28     Appendix E Power ISA sorted by opcode
  29     Appendix F Power ISA sorted by version
  30     Appendix G Power ISA sorted by Compliancy Subset
  31     Appendix H Power ISA sorted by mnemonic
  32 ```
  33
  34 **Summary**
  35
  36 ```
  37     Instructions added
  38     setvl    - Cray-style "Set Vector Length" instruction
  39     svstep   - Vertical-First Mode explicit Step and Status
  40     svremap  - Re-Mapping of Register Element Offsets
  41     svindex  - General-purpose setting of SHAPEs to be re-mapped
  42     svshape  - Hardware-level setting of SHAPEs for element re-mapping
  43     svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
  44 ```
  45
  46 **Submitter**: Luke Leighton (Libre-SOC)
  47
  48 **Requester**: Libre-SOC
  49
  50 **Impact on processor**:
  51
  52 ```
  53     Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  54     Management Instructions.
  55 ```
  56
  57 **Impact on software**:
  58
  59 ```
  60     Requires support for new instructions in assembler, debuggers,
  61     and related tools.
  62 ```
  63
  64 **Keywords**:
  65
  66 ```
  67     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
  68     Scalable Vectors
  69 ```
  70
  71 **Motivation**
  72
  73 TODO
  74
  75 **Notes and Observations**:
  76
  77 1. TODO
  78
  79 **Changes**
  80
  81 Add the following entries to:
  82
  83 * the Appendices of Book I
  84 * Instructions of Book I as a new Section
  85 * SVL-Form of Book I Section 1.6.1.6 and 1.6.2
  86
  87 ----------------
  88
  89 \newpage{}
  90
  91 # Vertical-First Stepping and status
  92
  93 SVL-Form
  94
  95 * svstep RT,SVi,vf (Rc=0)
  96 * svstep. RT,SVi,vf (Rc=1)
  97
  98 | 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
  99 |----|----|-----|------|----------|-------|--|--------- |
 100 |PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |
 101
 102 Pseudo-code:
 103
 104 ```
 105     if SVi[3:4] = 0b11 then
 106         # store subvl, pack and unpack in SVSTATE
 107         SVSTATE[53] <- SVi[5]
 108         SVSTATE[54] <- SVi[6]
 109         RT <- [0]*62 || SVSTATE[53:54]
 110     else
 111         step <- SVSTATE_NEXT(SVi, vf)
 112         RT <- [0]*57 || step
 113
 114 ```
 115
 116 Special Registers Altered:
 117
 118     CR0                     (if Rc=1)
 119
 120
 121 -------------
 122
 123 \newpage{}
 124
 125 # DX-Form
 126
 127 Add the following to Book I, 1.6.1.6, DX-Form
 128
 129 ```
 130     |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 131     | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
 132     | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
 133 ```
 134
 135 * Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
 136 * Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
 137 * Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
 138 * Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
 139
 140
 141 # Appendices
 142
 143     Appendix E Power ISA sorted by opcode
 144     Appendix F Power ISA sorted by version
 145     Appendix G Power ISA sorted by Compliancy Subset
 146     Appendix H Power ISA sorted by mnemonic
 147
 148 | Form | Book | Page | Version | mnemonic | Description |
 149 |------|------|------|---------|----------|-------------|
 150 | SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status |
 151