1 # RFC ls008 SVP64 Management instructions
7 * <https://libre-soc.org/openpower/sv/>
8 * <https://libre-soc.org/openpower/sv/rfc/ls008/>
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
10 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
22 **Books and Section affected**:
25 Book I, new Scalar Chapter. (Or, new Book on "Zero-Overhead Loop Subsystem")
26 Appendix E Power ISA sorted by opcode
27 Appendix F Power ISA sorted by version
28 Appendix G Power ISA sorted by Compliancy Subset
29 Appendix H Power ISA sorted by mnemonic
36 setvl - Cray-style "Set Vector Length" instruction
37 svstep - Vertical-First Mode explicit Step and Status
38 svremap - Re-Mapping of Register Element Offsets
39 svindex - General-purpose setting of SHAPEs to be re-mapped
40 svshape - Hardware-level setting of SHAPEs for element re-mapping
41 svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
44 **Submitter**: Luke Leighton (Libre-SOC)
46 **Requester**: Libre-SOC
48 **Impact on processor**:
51 Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
52 Management Instructions which can be implemented extremely efficiently
53 and effectively by inserting an additional phase between Decode and Issue.
54 More complex designs are NOT adversely impacted and in fact greatly benefit
55 whilst still retaining an obvious linear sequential execution programming model.
58 **Impact on software**:
61 Requires support for new instructions in assembler, debuggers,
68 Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
69 Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
76 **Notes and Observations**:
82 Add the following entries to:
84 * the Appendices of Book I
85 * Instructions of Book I as a new Section
86 * SVL-Form of Book I Section 1.6.1.6 and 1.6.2
92 # svstep: Vertical-First Stepping and status reporting
96 * svstep RT,SVi,vf (Rc=0)
97 * svstep. RT,SVi,vf (Rc=1)
99 | 0-5|6-10|11.15|16..22| 23-25 | 26-30 |31| Form |
100 |----|----|-----|------|----------|-------|--|--------- |
101 |PO | RT | / | SVi | / / vf | XO |Rc| SVL-Form |
106 if SVi[3:4] = 0b11 then
107 # store subvl, pack and unpack in SVSTATE
108 SVSTATE[53] <- SVi[5]
109 SVSTATE[54] <- SVi[6]
110 RT <- [0]*62 || SVSTATE[53:54]
112 step <- SVSTATE_NEXT(SVi, vf)
117 Special Registers Altered:
131 * setvl RT,RA,SVi,vf,vs,ms (Rc=0)
132 * setvl. RT,RA,SVi,vf,vs,ms (Rc=1)
139 if ms = 1 then MVL <- VLimm[0:6]
140 else MVL <- SVSTATE[0:6]
142 if vs = 0 then VL <- SVSTATE[7:13]
143 else if _RA != 0 then
144 if (RA) >u 0b1111111 then
147 else VL <- (RA)[57:63]
148 else if _RT = 0 then VL <- VLimm[0:6]
149 else if CTR >u 0b1111111 then
152 else VL <- CTR[57:63]
153 # limit VL to within MVL
160 GPR(_RT) <- [0]*57 || VL
161 if ((¬vs) & ¬(ms)) = 0 then
162 # set requested Vertical-First mode, clear persist
166 Special Registers Altered:
176 The format of the SVSTATE SPR is as follows:
178 | Field | Name | Description |
179 | ----- | -------- | --------------------- |
180 | 0:6 | maxvl | Max Vector Length |
181 | 7:13 | vl | Vector Length |
182 | 14:20 | srcstep | for srcstep = 0..VL-1 |
183 | 21:27 | dststep | for dststep = 0..VL-1 |
184 | 28:29 | dsubstep | for substep = 0..SUBVL-1 |
185 | 30:31 | ssubstep | for substep = 0..SUBVL-1 |
186 | 32:33 | mi0 | REMAP RA SVSHAPE0-3 |
187 | 34:35 | mi1 | REMAP RB SVSHAPE0-3 |
188 | 36:37 | mi2 | REMAP RC SVSHAPE0-3 |
189 | 38:39 | mo0 | REMAP RT SVSHAPE0-3 |
190 | 40:41 | mo1 | REMAP EA SVSHAPE0-3 |
191 | 42:46 | SVme | REMAP enable (RA-RT) |
192 | 47:52 | rsvd | reserved |
193 | 53 | pack | PACK (srcstrp reorder) |
194 | 54 | unpack | UNPACK (dststep order) |
195 | 55:61 | hphint | Horizontal Hint |
196 | 62 | RMpst | REMAP persistence |
197 | 63 | vfirst | Vertical First mode |
201 * The entries are truncated to be within range. Attempts to set VL to
202 greater than MAXVL will truncate VL.
203 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
204 than 64 is reserved and will cause an illegal instruction trap.
212 Add the following to Book I, 1.6.1, SVL-Form
215 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
216 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
217 | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
220 * Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
221 * Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
222 * Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
223 * Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
225 Add the following to Book I, 1.6.2
229 Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
233 Field used in Simple-V to specify whether "Vertical" Mode is set
234 (vfirst in the SVSTATE SPR)
237 Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
240 Simple-V immediate field for setting VL or MVL (vl, maxvl in the SVSTATE SPR)
247 Appendix E Power ISA sorted by opcode
248 Appendix F Power ISA sorted by version
249 Appendix G Power ISA sorted by Compliancy Subset
250 Appendix H Power ISA sorted by mnemonic
252 | Form | Book | Page | Version | mnemonic | Description |
253 |------|------|------|---------|----------|-------------|
254 | SVL | I | # | 3.0B | svstep | Vertical-First Stepping and status reporting |